Abstract: An improved chopper stabilized operational amplifier is disclosed, along with an improved method of timing the switchings of chopper switches in such an amplifier. The disclosure includes an integrated circuit and method for generating a true random voltage signal having a truly random RMS voltage value within a selected range. The true random voltage signal is obtained by amplifying and bandpass filtering random white noise voltages generated by a component of the circuit. The white noise voltages include shot noise voltages generated by bipolar transistors in an input amplifier stage. The random signal generator circuit and method is employed with an oscillator to form a random clock signal generator on the integrated circuit chip. The amount of time between each clocking pulse output by the random clock signal generator truly randomly varies within a selected range of time, and repeats only by random chance.

Abstract: A method and digital system for testing scannable memory and combinational networks. The scannable memory is configurable into several scan chains. Each chain may have a different effective clock rate, as determined by respective clock enable signals. The method and digital system allow scan testing of digital circuits that use a single operational clock rate and several functional clock enable signals to effect slower lock operating rates. The digital system includes memory elements having scan enable and clock enable inputs.

Abstract: A method of making an integrated circuit package for EPROM, CCD, and other optical integrated circuit devices is disclosed. First, a substrate base having metallized vias extending there through is provided. Second, an integrated circuit die is affixed to a first surface of the substrate, and is electrically connected to the metallized vias. Third, a bead of a viscous adhesive material is applied onto the substrate around the device. The bead covers the side surfaces of the device, the periphery of the upper first surface of the device, and the bond wires. The bead and the upper first surface of the die form a cavity above the die. Fourth, a layer of a transparent encapsulating material is deposited onto the die, within the cavity formed by the bead. Fifth, the encapsulating material is hardened, and subsequently forms an exterior surface of the package. The transparent encapsulating material allows light to illuminate the light sensitive circuitry of the device.

Abstract: An organohydridosiloxane polymer having a cage conformation, at least approximately 40 Mole percent carbon containing substituents and a dielectric constant of less than about 2.7 is presented. Each silicon atom of the cage polymer is bonded to at least three oxygen atoms and to either a hydrogen atom or an organic substituent. By providing such a caged structure with essentially no hydroxyl or alkoxy substituents, either on the polymer backbone or at terminal silicon atoms, essentially no chain lengthening polymerization can occur in solution. Such organohydridosiloxane resins having a molecular weight in the range from about 400 to about 200,000 atomic mass units were formed using a dual phase solvent system and either a solid phase or phase transfer catalyst to assist the condensation of hydridotrihalosilane with at least one organotrihalosilane.

Abstract: A method and system for receiving a signal in a received frequency and shifting the received frequency to become a desired frequency is provided. The system includes a controllable oscillator for generating a first internal frequency, a frequency estimating unit connected to the controllable oscillator, a first frequency shift unit, connected to the controllable oscillator and to the frequency estimating unit, for shifting the received frequency according to the first internal frequency, thereby obtaining an initially shifted frequency and a second frequency shift unit connected to the first frequency shift unit and the frequency estimating unit for shifting the initially shifted frequency. The frequency estimating unit determines a total frequency shift value from the desired frequency, the received frequency and the first internal frequency and it also determines a first frequency shift value and a second frequency shift value from the total frequency shift value.

Abstract: A door lock device having an indoor and outdoor housing, each having inner tube-shaped supports, and further including indoor and outdoor handle connection members, each having at a first end handle connections with an indoor and an outdoor handle, respectively, and having at a second end opposite the first end driving cams formed with a cam curvature having step differences in an axial direction. Indoor and outdoor slide cylinders are provided having driven cams in contact with the driving cams and experiencing a rectilinear motion in the axial direction by means of the axial step difference. A first coupling spring is fixed to the indoor handle connection member and the indoor slide cylinder. A second coupling spring is fixed to the outdoor handle connection member and the outdoor slide cylinder. Indoor and outdoor end frames allow the indoor and outdoor slide cylinders to be guided rectilinearly in the axial direction by means of a rectilinear guide fitting.

Abstract: An electron-emitting device contains a vertical emitter resistor patterned into multiple laterally separated sections (34, 34V, 46, or 46V) situated between the electron-emissive elements (40), on one hand, and emitter electrodes (32), on the other hand. Sections of the resistor are spaced apart along each emitter electrode.

Abstract: Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant.A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.

Abstract: A getter (50) situated in a cavity of a hollow structure (40-46), such as a flat-panel device, is activated by directing light energy locally through part of a hollow structure and onto the getter. The light energy is typically provided by a laser beam (60). The getter, typically of the non-evaporable type, is usually inserted as a single piece of gettering material into the cavity. The getter normally can be activated/re-activated multiple times in this manner, typically during the sealing of different parts of the structure together.

Abstract: A polysilicon-based floating gate is formed so as to be resistant to oxidation that occurs during multiple thermo-cycles in fabrication. Accordingly, edge erase times in NOR-type memory devices may be minimized. Additionally, manufacture of oxidation resistant floating gates reduces variations in edge erase times among multiple NOR-type memory devices. A layer of amorphous silicon is deposited on a silicon substrate by directing silane, a phosphene and helium gas mixture, and ammonia at the surface of the silicon substrate thereby doping the amorphous silicon in situ. The amorphous silicon layer is then etched so as to overlap slightly with regions that will later correspond to the source and drain regions. Next, a lower oxide layer of an ONO dielectric is deposited and the device is heated. A thermo-cycle is eliminated by heating the amorphous silicon during formation of the oxide layer rather than immediately following its deposition.

Abstract: A driver circuit (18) generates a circuit output signal (V.sub.DO) which is provided to an electrical conductor (12) that furnishes a conductor output signal (V.sub.BO) to a load (14). The circuit and conductor output signals make corresponding circuit and conductor output transitions approximately between a pair of output voltage levels (V.sub.SS and V.sub.DD) between which there is an intermediate voltage level (V.sub.HH). Inductance (LB) and capacitance (CB and CL) of the conductor and load produce resonance that enables the conductor output signal to largely complete each conductor output transition while the circuit output signal is being held at or close to the intermediate voltage level for a short period. The circuit output signal rapidly completes each circuit output transition after the intermediate-level holding period is over. By operating in this manner, energy is re-used in a resonant manner, thereby substantially reducing power consumption.

Abstract: An assembly process provides a chip scale package (CSP) which characteristically includes (i) a perforated substrate in which vias can be embedded, (ii) a solder mask on which the integrated circuit die can be attached, and (iii) efficient use of the surface area for electrically routing signals from the integrated circuit die to the external terminals attached to the perforated substrate. The resulting package is highly compact and therefore has a foot print minimally larger than the surface area of the integrated circuit chip. Consequently, the costs of substrate and capsulation materials are minimized. The assembly process allows very high volume production because a large number of integrated circuits can be made on a single unit of the substrate, and singulation is performed in the assembly process at a stage much later than the corresponding stage in a conventional process.

Abstract: An apparatus for electroplating a wafer surface includes a cup having a central aperture defined by an inner perimeter, a compliant seal adjacent the inner perimeter, contacts adjacent the compliant seal and a cone attached to a rotatable spindle. The compliant seal forms a seal with the perimeter region of the wafer surface preventing plating solution from contaminating the wafer edge, wafer backside and the contacts. As a further measure to prevent contamination, the region behind the compliant seal is pressurized. By rotating the wafer during electroplating, bubble entrapment on the wafer surface is prevented. Further, the contacts can be arranged into banks of contacts and the resistivity between banks can be tested to detect poor electrical connections between the contacts and the wafer surface.

Abstract: A just-in-time (JIT) compiler typically generates code from bytecodes that have a sequence of assembly instructions forming a "template". It has been discovered that a just-in-time (JIT) compiler generates a small number, approximately 2.3, assembly instructions per bytecode. It has also been discovered that, within a template, the assembly instructions are almost always dependent on the next assembly instruction. The absence of a dependence between instructions of different templates is exploited to increase the size of issue groups using scheduling. A fast method for scheduling program instructions is useful in just-in-time (JIT) compilers. Scheduling of instructions is generally useful for just-in-time (JIT) compilers that are targeted to in-order superscalar processors because the code generated by the JIT compilers is often sequential in nature.

Abstract: A power MOSFET includes a trenched gate which defines a plurality of MOSFET cells. A protective diffusion is created, preferably in an inactive cell, so as to form a diode that is connected in parallel with the channel region in each of the MOSFET cells. The protective diffusion, which replaces the deep central diffusion taught in U.S. Pat. No. 5,072,266, prevents impact ionization and the resulting generation of carriers near the corners of the gate trench, which can damage or rupture the gate oxide layer. Moreover, the diode can be designed to have a breakdown voltage which limits the strength of the electric field across the gate oxide layer. The elimination of a deep central diffusion permits an increase in cell density and improves the on-resistance of the MOSFET. Specifications for a number of commercially acceptable devices are given.

Abstract: A method for distributing the available bit rates in a variable bit rate service under asynchronous transfer mode is provided by distributing the available bit rates in logarithmic-linear steps, so that the ratio between two successive available bit rates are substantially constant. To minimize computation required to calculate the next available allowable cell rate, a table look-up method can be used in conjunction with a state machine. In one embodiment, the table look-up operation includes accessing a rate increase table and a rate decrease table. A selection circuit is provided to choose the next allowable cell rate from the current cell rate, and the output values obtained from looking up the rate increase table and the rate decrease table.

Abstract: A structure wherein a hand held computer module can be conveniently and interchangeably coupled to accessory devices. The hand held computer module is detachably connected to a first accessory module by a first interlocking structure. The computer module includes the first interlock mechanism and the first accessory module includes the second interlock mechanism. The first and second interlock mechanisms are mated together to form a physical connection between the computer module and the first accessory module. The first accessory module also includes a third interlock mechanism which is similar to the first interlock mechanism. A second accessory module has a fourth interlock mechanism which is similar to the second interlock mechanism. The first accessory module can be detachably connected to a second accessory module by means of a second interlocking structure which includes the third and fourth interlock mechanisms.

Abstract: A method for manufacturing integrated circuits increases the aspect ratio of the electrical conductor members connected to the circuits by increasing the effective height of the conductors, either by forming a thicker layer of conductor material prior to patterning the conductor members, or by adding a capping dielectric layer to the conductor material prior to patterning, or by overetching the dielectric material underlying the conductor members.The structure is then covered by a dielectric layer having poor step coverage, resulting in a number of voids and open spaces in the dielectric layer to thereby reduce the dielectric constant between the patterned conductors. A plasma etchback of the dielectric layer is employed to open and shape additional voids and open spaces in the dielectric layer. This is followed by the deposition of a second layer of dielectric material to seal the structure, including any open spaces in the first layer of dielectric material.

Abstract: A two-axis stage assembly includes a generally planar horizontally mounted base plate; a stage plate generally parallel to the base plate, the stage plate having a first axis and second orthogonal axis; a set of spaced bearings depending from a bottom surface of said stage plate, the bearings each having an arcuate bottom surface in rocking contact with a facing support surface of the base plate; a joint attached to the bottom surface of the stage plate and pivotably mounting each bearing, the joint being positioned at the center of curvature of the arcuate bottom surface of the associated bearing; and where an axial movement of the stage plate rocks the bearing arcuate bottom surfaces with respect to the facing support surface of the base plate.

Abstract: In accordance with this invention, a data capture circuit of a data receiver captures data from a data stream of a data transmitter operating at a different phase or frequency from the system clock of the data receiver. In one embodiment, the data receiver determines the number of clock periods of a clock signal in a data period of the data stream. Specifically, a signal detection circuit receives a signal having a periodic and distinctive feature. The period of the periodic and distinctive feature is related to the data period by a fixed scaling factor. A counter counts the number of clock periods of the clock signal between a first occurrence of the periodic and distinctive feature and a second occurrence of the periodic and distinctive feature. A multiplier/divider circuit divides or multiples the content of the first counter by the scaling factor to determine the integer clock period count. The results of the multiply or divide is stored in a count register.