Abstract: A method for selectively forming a dielectric layer. An embodiment includes forming a dielectric layer, such as an oxide layer, on a semiconductor substrate, depositing a silicon layer on the dielectric layer, and treating the silicon layer with nitrogen, thereby converting the silicon layer into a silicon nitride layer. This method allows for a protective silicon nitride layer to be formed, while also preventing and/or reducing the nitrogen itself from penetrating far enough to contaminate the substrate. In another embodiment the treating with nitrogen is continued to form not only a silicon nitride, but to also diffuse a small portion of nitrogen into the dielectric layer to nitridized a portion of the dielectric layer. Optionally, an anneal could be performed to repair any damage that has been done by the treatment process.

Abstract: A method for listening to signal tone from a called party by a calling party during network interworking. When the media gateway control unit receives an Address Complete message or Call Progress message from the circuit domain network, the media gateway control unit instructs a media gateway to open a media stream channel. If the received message carries an indicator indicating the called party is free, the media gateway control unit sends a Ringing response message to the packet core network; if the received message does not carry a indicator indicating the called party is free, the media gateway control unit sends a response message carrying indicator of failed call but successful media stream setup or a response message indicating failed call but successful media stream setup to the packet core network. With the method according to the embodiments of the present invention, the calling party may hear ring-back tone indicating successful call, or signal tone or voice announcement indicating failed call.

Abstract: A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.

Abstract: A method for processing a Buffer Status Report (BSR) is provided, which includes: acquiring service data with a higher priority than all service data waiting to be sent in a sending buffer; and prohibiting a sending process of the BSR from being triggered, if scheduling resources are available. An apparatus for processing a BSR is further provided.

Abstract: Circuits and methods for providing a floating gate structure comprising floating gate cells having improved reverse tunnel disturb immunity. A floating gate structure is formed over a semiconductor substrate comprising a floating gate, a charge trapping dielectric layer is formed, and a control gate is formed. The floating gate structure has vertical sidewalls, one side adjacent a source region and one side adjacent a drain region. A symmetric sidewall dielectric is formed over the floating gate structure on both the source side and drain side regions. An asymmetric dielectric layer is formed over the drain side sidewall only. The use of the asymmetric sidewall on the drain side sidewall provides improved RTD immunity. Methods for forming the structure are disclosed.

Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

Abstract: An embodiment is a semiconductor device comprising a receiver circuit comprising fin field effect transistors (FinFETs), a transceiver circuit comprising FinFETs, and a transmit bus electrically coupling the receiver circuit and the transceiver circuit, wherein the receiver circuit and the transceiver circuit each further comprises an electrostatic discharge protection circuit comprising planar transistors electrically coupled to the transmit bus. Other embodiments may further comprise a power clamp electrically coupling a first power bus and a first ground bus, a power clamp electrically coupling a second power bus and a second ground bus, or at least two diodes electrically cross-coupling the first ground bus and the second ground bus. Also, the planar transistors of the transceiver circuit and the receiver circuit may each comprise a planar PMOS transistor and a planar NMOS transistor.

Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.

Abstract: A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach.

Abstract: A system and method for uplink inter cell interference coordination and multi-user multiple input, multiple output in a wireless access system are provided. A method for providing uplink inter cell interference coordination in a wireless access system includes categorizing users the wireless access system, selecting a resource allocation plan based on the categorized users, allocating resources to the users in the wireless access system based on the selected resource allocation plan, and receiving transmissions from the users.

Abstract: System and method for dynamic resource allocation in wireless communications networks. A method for dynamically allocating resources of a contention channel comprises computing an expected delay for a transmission made by a user over the contention channel, determining a target probability of collision from the expected delay, computing an allocation of resources of the contention channel using the target probability of collision, and allocating resources of the contention channel using the computed allocation of resources.

Abstract: A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.

Abstract: A lithography system with a stray light feedback system is disclosed. The stray light feedback helps control critical dimension (CD) within a stray light specification limit. A stray light dose control factor is calculated as a function of the stray light measured in the exposure tool and the sensitivity of the resist. The stray light dose control factor is used to adjust the exposure dose to achieve the desired CD. The stray light may be monitored, and if a threshold level of stray light is reached or exceeded, the use of the exposure tool may be discontinued for a particular type of semiconductor product, resist, or mask level, until the lens system is cleaned.

Abstract: A method for performing a clock and data recovery includes providing data and a clock; determining early/late values of the data to generate a first-order phase code using the data and the clock; and accumulating first-order phase codes retrieved from different finite state machine (FSM) cycles to generate a second-order phase code. A plurality of candidate total phase codes is generated from the second-order phase code. A multiplexing is performed to the plurality of candidate total phase codes to output one of the plurality of candidate total phase codes as a total phase code. The multiplexing is controlled by the first-order phase code. A brake machine may be implemented to prevent over-compensation of phases.

Abstract: An electric organic component and a method for the production thereof is disclosed. The component includes a substrate, a first electrode, a first electrically semiconductive layer on the first electrode, an organic functional layer on the first electrically semiconductive layer and a second electrode on the organic functional layer. The first or the second electrode may be arranged on the substrate. The electrically semiconductive layer is doped with a dopant which comprises rhenium compounds.

Abstract: The invention relates to a circuit unit for driving an electronically commutated fan motor with a power stage for driving windings of the fan motor and with a control stage for driving the power stage. The circuit unit is distinguished in that an operating voltage of the control stage is separated from an operating voltage of the power stage by a diode and in that an arrangement is provided for smoothing the operating voltage of the control stage.

Abstract: A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Methods for producing integrated circuits are disclosed forming programmable transistor arrays and implementing customer specified system designs upon the programmable transistor arrays.

Abstract: A method, a system, and an apparatus for improving throughput performance of an SDMA system are disclosed herein. The method includes BTS receiving feedback information sent by a UE, where the feedback information comprises an ID of a preferred beam of the UE in a pre-coding codebook, information related to a channel vector modulus value, and information about phase difference between a channel vector and the preferred beam of the UE, and the BTS using a set estimation algorithm to estimate sum throughputs supported by a current SDMA system in each sending mode according to the received feedback information and information about space correlation between multiple antennas of the BTS, selecting a maximum sum throughput among the estimated sum throughputs, and using the sending mode corresponding to this sum throughput to send data. The method, system, and apparatus provided herein improve transmitting performance of the SDMA system.

Abstract: The invention relates to an antenna which is coupled to an RF amplifier. Environmental conditions change the impedance of the antenna, which reduces output power, efficiency and linearity. A circuit is provided which is designed to detect the impedance of the antenna. With the measured impedance, impedance matching can be accomplished. The circuit for detecting the impedance detects the signal travelling from the RF amplifier to the antenna, and measures the peak voltage and the peak current of this signal. Furthermore, the phase difference between the voltage and the current is measured. The advantage of the circuit is its compactness allowing for an easy integration on a chip. Furthermore, an impedance matching circuit is suggested which makes use of the above circuit for detecting the impedance.

Abstract: An integrated circuit chip includes a first electronic device, a second electronic device, and a common electrode feature. The first electronic device includes a first feature. The first electronic device has a first footprint area in a given layer. The second electronic device includes a second feature. The second electronic device has a second footprint area in the given layer. The first and second electronic devices are electrically matched. The common electrode feature is common to the first and second electronic devices. The common electrode is at least partially located in the given layer. More than a majority of the first footprint area overlaps with the second footprint area. A first spacing between the first feature and the common electrode feature is about the same as a second spacing between the second feature and the common electrode feature.