Abstract: A carrier injected dynamic random access memory is defined. A depletion region adjacent to a source/drain region of a transistor is used as a storage cell in a memory array, and logic levels may then be measured by sensing the conductive portion. A low logic level is stored by a reduced formation of the depletion adjacent the conductive portion. These logic levels are sensed and periodically refreshed by conduction through the access device. The logic levels may be read by measuring potential through the access device, or by measuring punch through voltage between the source/drain region and a nearby conductive region. As the level of injected carriers increases, the punch through also increases. A punch through results in a readable increase in current through the access device, thereby providing an indicia of a in logic level.

Abstract: A process and structure for improving the conductive capacity of a polycrystalline silicon (poly) structure, such as a bit line. The inventive process allows for the formation of a refractory metal silicide layer on the top and sidewalls of a poly structure, thereby increasing the conductive capacity. To form the titanium silicide layer over the poly feature, the refractory metal is sputtered on the poly, which reacts to form the refractory metal silicide. A second embodiment is described whereby an isotropic etch of the poly feature slopes the sidewalls; then, the refractory metal is sputtered onto the polycrystalline silicon. This allows for the formation of a thicker layer of refractory metal silicide on the sidewalls, thereby further increasing the conductive capacitance of the poly structure. Suggested refractory metals include titanium, cobalt, tungsten, and tantalum.

Abstract: A semiconductor assembly comprises a semiconductor die which is attached by a carrier material to a lead frame. The carrier material is coated on the die side with one type of adhesive and on the lead frame side with a different adhesive. The lead frame has a small surface area to connect to the carrier material, while the semiconductor die has a large surface area to connect to the carrier material. As used with one inventive embodiment, the adhesive between the die and the carrier softens at a low temperature preventing the die from cracking at elevated temperatures. The adhesive on the lead frame side of the carrier material softens at a higher temperature than the adhesive of the die side of the adhesive, thereby firmly connecting the lead frame having a small surface area to the carrier.

Abstract: A reusable burn-in/test fixture for discrete die consists of two halves. The first half of the test fixture contains cavity in which die is inserted. When the two halves are assembled, the fixture establishes electrical contact with the die and with a burn-in oven. The test fixture need not be opened until the burn-in and electrical test are completed. The fixture permits the die to be characterized prior to assembly.

Abstract: A Flash EPROM cell having buried source-side injection is disclosed which allows for low voltage programming from the source side. A cell having the inventive structure can be programmed at 4.0 V or less.The inventive cell comprises a source area which is at a lower plane than the drain region, and a program charge is transferred to the floating gate through the source-side injector. Instead of using a self-aligned high-energy n-type dopant implant at the source side to form the source side injector as used with previous cells, which can be difficult to control, etching the substrate before doping it with impurities allows for the controllable formation of a sharp point of doped silicon, and allows for improved programming at a lower voltage.

Abstract: Described is a process used during the formation of a semiconductor device to produce a doped layer of polycrystalline silicon having a pair of conductivity types using a single mask step. In a first embodiment, a patterned nonoxidizing layer is formed over the layer of polycrystalline silicon thereby leaving protected and exposed poly. The exposed polycrystalline silicon is doped, then oxidized, with the protected poly being free of oxidation. The nonoxidizing layer is stripped, and a blanket implant is performed. The oxidation prevents the previously doped polycrystalline silicon from being counterdoped. The oxidation is then stripped and wafer processing continues. In a second embodiment, a layer of resist is formed over the polycrystalline silicon layer, and the exposed poly is heavily doped with a material having a first conductivity type. The resist is removed, and the surface is blanket doped with a material having a second conductivity type.

Abstract: A temperature sensing circuit allows a DRAM array to use less power than would normally be possible due to the reduced refresh rate based on the temperature of the DRAM array. The temperature circuit removes the refresh guardbanding on the DRAMS. Instead of refreshing a 1 megabyte DRAM every 8 ms, refreshing the DRAMs every 128 ms is possible, depending on the temperature of the DRAM array.

Abstract: A dynamic random access memory (DRAM) array is configured to appear to a host computer as a static random access memory (SRAM) array. This allows the use of a component which is functionally equivalent to an SRAM array, but which is less costly and which provides more memory in the same unit area. A temperature sensing circuit allows the DRAM array to use less power than would normally be possible by using a reduced refresh rate based on the temperature of the DRAM array. For example, instead of refreshing a 1 megabyte DRAM every 8 ms, refreshing the DRAM every 128 ms is possible, depending on the temperature of the DRAM array.

Abstract: A method to anisotropically etch an oxide/metalsilicide/polysilicon sandwich structure on a silicon wafer substrate in situ, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a metalsilicide/polysilicon etch step. The fully etched sandwich structure has a vertical profile at or near 90.degree. from horizontal, with no bowing or notching.

Abstract: A process for fabricating n-channel and p-channel metal-oxide-semiconductor devices in the manufacture of very large scale integrated circuits, such as high density dynamic random access memories (DRAMs). n-channel and p-channel gate layers of selected conductive and non-conductive materials are initially formed on the surface of a semiconductor substrate, and the n-channel gate layers in a memory array and periphery section of the substrate are initially photodefined, leaving the p-channel gate layers in place over an area of the substrate where future p-channel transistors and P+ active area will be formed. A series of ion implantation steps are then carried out to form the n-channel transistors, therefor using no masking steps, since the in-place gate layers on the p-channel peripheral section serves as an ion implantation mask over this section and thus prevents n-type ions from entering the p-type transistor areas of the peripheral section.

Abstract: A process and structure for an electrically erasable programmable read-only memory is described. The PROM is manufactured with four poly layers, the poly layers forming the floating and control gates, a structure coupling isolated source areas, and the fourth layer forming the digit lines. The inventive structure allows for a self-aligned poly source line which removes the need for an etch of the field oxide which is required in conventional EEPROM designs, which are known to be difficult to control. The poly digit line is also self-aligned and has a large margin of misalignment error in an etch to expose the drain region of the substrate.

Abstract: Implantation of germanium (45) into a PMOS buried channel to permits the enhancement implant profile (to 45) to be made more shallow. The shallow profile will reduce or eventually solve P-channel buried channel-induced short channel effects and enable further decrease in device length to deep submicron range.Benefits include better short channel characteristics, i.e., higher punch through voltage BVDSS, less V.sub.T sensitivity to the drain voltage (defined as curl) and better subthreshold leakage characteristics.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.cc power bus and the other node directly V.sub.ss power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.

Abstract: A multichip module (MCM) is formed with external connections on coaxial pins. This provides an impedance between a ground connection and a signal connection which is substantially equal per unit length. The module may be configured so that the impedances of the connections between the signal connections and integrated circuit may also be optimally impedance matched.

Abstract: Described is an E.sup.2 PROM design comprising a channel region and a floating gate comprising P-type polycrystalline silicon. The work function difference between P-type material effectively increases the threshold voltage of the transistor. This alleviates the need for a boron V.sub.T adjust implant. Implants of material such as boron to set the threshold voltage are known to correlate with problems such as implant ionization and junction (avalanche) breakdown. These two undesired effects can be decreased or eliminated in devices comprising the invention. An optional phosphorous implant into the substrate would allow the lowering of V.sub.T to a desired level.

Abstract: A lead frame design which can be used with a number of different die sizes is described. To customize the lead frame, a punch excises an amount of lead finger material to form a void between the lead fingers for receiving a die. The amount of material removed is greater for larger sized die. A material, such as an adhesive tape, attaches the die to the lead frame. The bond pads on the die are then wire bonded to the lead fingers. The adhesive tape also locks the lead fingers into place, thereby preventing movement which could detach the bond wires from the die or lead frame.

Abstract: A memory module for an electronic device is disclosed which provides means for reducing the amount of power necessary to access a desired number of data bits. This provides a design of memory modules which requires fewer DRAMs to be turned on during a read or write cycle than present module designs, thereby using much less power.

Abstract: Disclosed is a process step performed during a wafer etch which allows for the formation of more vertical sidewalls. During a conventional etch step of a material such as oxide, oxygen is released into the etch chamber, which is known to adversely affect the vertical profile of the sidewalls. The oxygen is known to combine with silicon and HBr, which are present as gasses within the etch chamber during the subsequent poly etch, to deposit on the poly sidewalls. For this reason subsequent etches are conventionally performed in a separate etch chamber.The disclosed step introduces an oxygen-scavenging gas into the etch chamber prior to the subsequent etch of the polycrystalline silicon. The oxygen-scavenging gas combines with the liberated oxygen with the application of plasma energy to produce an inert volatile gas which can be pumped from the etch chamber and therefore not adversely affect subsequent etches. Claimed oxygen-scavenging gasses include C.sub.2 F.sub.6, CF.sub.4, CHF.sub.3, and BCl.sub.3.

Abstract: A CMOS integrated circuit such as a DRAM is fabricated, in which a first layer of polysilicon is used to form transistor gates, and capacitor cell plates are formed from a second polysilicon layer.N-wells are first formed, followed by initial oxide. The application of the CMOS process to the reverse poly technique provides enhanced alignment of critical transistor gates and permits the use of less mask steps in fabricating the CMOS circuit.

Abstract: A wirebond probe head is modified for use in forming raised portions from material. The modified head includes a main portion and a sleeve, with the sleeve functioning as a shroud to reduce the tendency of forged material to exude from the periphery of the wirebond probe. The sleeve may also be vibrationally isolated from the main portion of the head in order to attenuate vibrational energy transferred from the main portion of the head to the sleeve. The inventive head functions by being brought into close proximity to a surface material and applying energy. This results in an ultrasonically formed elevated surface irregularity, or an ultrasonic forging splash, which useful as an electrical contact pad for permanent and semipermanent electrical connections.