Abstract: A method is provided for pre-tabulating sub-networks that (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements or performs a set of two or more functions. Some embodiments provide a method for producing a circuit description of a design that (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the replacement sub-network in certain conditions. Some embodiments provide a data storage structure that stores a plurality of sub-networks based on parameters derived from the output functions of the sub-networks.

Abstract: Some embodiments of the invention provide a method of routing several nets in a region of a design layout. Each net includes a set of pins in the region. In some embodiments, the method partitions the region into several sub-regions that have a number of edges between them. The method (1) for each particular net and each particular edge, identifies an edge-intersect probability that specifies the probability that a set of potential routes for the particular net will intersect the particular edge, and (2) uses the identified edge-intersect probabilities to identify routes for the nets. A potential route for a particular net traverses the set of sub-regions that contain the particular net's set of pins. In other embodiments, the method partitions the region into several sub-regions that have a number of paths between them.

Abstract: One embodiment of the invention is a method of routing a group of nets in a region. The method identifies a first route for a first net. It then determines whether embedding the first route in the region will make a set of unrouted nets in the region unroutable. When embedding the first route will make the set of unrouted nets unroutable, the method then identifies a second route for the first net. If embedding a route will not make the set of unrouted nets unroutable, the method embeds the route in the region.

Abstract: Some embodiments of the invention provide a method of identifying routes in a region of an integrated circuit (“IC”) design layout. The region contains at least one net with several routable elements. The method decomposes the IC design-layout region into a tessellated graph. The tessellated graph includes a plurality of edges. The method then specifies a route that connects the net's routable elements by specifying a set of edges that the route intersects.

Abstract: Some embodiments of the invention provide a method of propagating a first cost function that is defined over a first state to a second slate in a space representing a design-layout region. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. The space has several dimensional states. The method identifies several pairs of wedge vectors. Each vector has a tail, and each wedge-vector pair includes two vectors that are connected at their tails. The method assigns locations in the first state for the tails of at least some of the identified wedge-vector pairs. The method then uses the wedge-vector pairs that have assigned tail locations to propagate the first cost function.

Abstract: Some embodiments of the invention provide a method of routing nets in an integrated-circuit layout region that has multiple interconnect layers. The method specifies several routes, where some of the routes utilize vias to traverse multiple interconnect layers. The method assesses a cost of at least one via proportionately to a cost that the via introduces in the design of the integrated circuit.

Abstract: A discrete inductive-capacitive (LC) filter selects between at least two inductor banks to tune the LC filter. The filter receives an input signal that includes one or more bands of frequencies. A control signal selects a band of frequencies for processing. A first inductor bank is selected to filter a first band of frequencies, and a second inductor bank is selected to filter a second band of frequencies. A switch circuit couples the input signal to either the first inductor bank or the second inductor bank. The switch circuit selects the first inductor bank if the first band of frequencies is selected, and selects the second inductor bank if the second band of frequencies is selected. The switch circuit electrically isolates the switching of the input signal to the first and the second inductor banks, so as to enhance the Q factor of the LC filter. Circuit and techniques are disclosed to reduce parasitic capacitance in a capacitive bank that employs MOS transistors.

Abstract: The present invention introduces novel methods of performing integrated circuit layout extraction. In the system of the present invention, a complex extraction problem is first broken down into a set of smaller extraction sub problems. Some of the smaller extraction sub problems may be handled by simple parametric models. For example, extracting the resistance from a straight section of interconnect wire may be performed by multiplying a known resistance per unit length by the length of the straight section of interconnect wire. For more complex extraction sub problems, machine learning is used to build models. In one embodiment, Support Vector Machines are constructed to extract the desired electrical characteristics.

Abstract: Some embodiments of the invention provide a method of routing nets in a region of a design layout. The region contains a plurality of nets and has multiple interconnect layers. The method identifies routes for a set of nets in the region, where some of the routes utilize vias to traverse multiple interconnect layers. The method then moves at least one via to improve the routing.

Abstract: For a path search that identifies a path between source and target states in a space, some embodiments of the invention provide a method for determining viability of an expansion of a path from a first state to a second dimensional state. The method computes a first cost function that expresses the cost of the path to reach the second state. The first cost function is defined over the second state. The method then determines whether the first cost function expresses a better cost over any portion of the second state than a second cost function that expresses the best cost of paths that have reached the second state during the path search. The expansion is a viable one if the first cost function expresses a better cost over at least a portion of the second state than the second cost function.

Abstract: Some embodiments of the invention provide a path-searching method. This method identifies two sets of states in a multi-state space, where at least some of the states have at least one dimension. It then performs an epsilon-optimal path search to identify an epsilon-optimal path between the two set of states. The epsilon-optimal path is a path that is within an epsilon of the optimal path between the two sets of states. During the espsilon optimal search, the method propagates a cost function that is defined over one state to another state.

Abstract: A routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.

Abstract: Some embodiments of the invention provide an integrated circuit (“IC”) design layout that includes topological routes. This layout includes several nets, each with a set of routable elements in the IC design-layout region. For each net, this layout also includes a topological route that connects the net's routable elements. Each topological route is a route that represents a set of diffeomorphic geometric routes. In some embodiments, the IC layout further includes a topological graph that represents the IC design layout topologically. The topological graph includes several topological items including a set of items for each net that represent the net's routable elements. Each net's topological route specifies an associated set of items in the topological graph.

Abstract: The present invention introduces novel methods of performing integrated circuit layout extraction. In the system of the present invention, a complex extraction problem is first broken down into a set of smaller extraction sub problems. Some of the smaller extraction sub problems may be handled by simple parametric models. However, for the frequent complex extraction sub problems, machine learning is used to build models. Specifically, Support Vector Machines are constructed to extract the desired electrical characteristics. To build the Support Vector Machines, Experimental design is employed to select a set of training points that provide the best information. In one embodiment, the training point set is created by creating a critical input spanning set, adding training points from critical regions in the input space, and adding training points from frequently encountered profile cases.

Abstract: An unlicensed wireless communication base station includes a radio frequency circuit to transmit an unlicensed wireless communication base station identification signal to a subscriber device and to receive licensed wireless communication system security information from the subscriber device responding to the unlicensed wireless communication base station identification signal. A control circuit is connected to the radio frequency circuit. Network interface circuitry is connected to the control circuit. The control circuit conveys the licensed wireless communication system security information to the network interface circuitry for delivery to a network. The network interface circuitry receives from the network an authentication command that is delivered to the control circuit. The control circuit and the radio frequency circuit coordinate unlicensed wireless communication between the subscriber device and the unlicensed wireless communication base station in response to the authentication command.

Abstract: A method for modeling a substrate, which includes obtaining vertically discretized doping profiles in the substrate to facilitate modeling. The method includes employing substrate region names and substrate cross-section names as access keys to permit accessing of the vertically discretized doping profiles. The use of the combination of region names and substrate cross-section names as unique access keys simplifies access to doping profile information for modeling purposes and yields valuable information pertaining to the presence of p-type to n-type material transitions. The information pertaining to transitions may be employed to improve substrate modeling accuracy through the inclusion of junction capacitances with the modeling process.

Abstract: The present invention introduces several methods for implementing arbitrary angle wiring layers for integrated circuit manufacture with simulated Euclidean wiring. Entire routing layers may be implemented with arbitrary angle preferred wiring using simulated Euclidean wiring. In a first embodiment, the arbitrary angle wiring layers are created by routing arbitrary angle wires created from a selected ratio alternating segments of horizontal interconnect wire segments and vertical interconnect wire segments. In another embodiment, the arbitrary angle wiring layers are created by routing arbitrary angle wires created from a selected ratio alternating segments of horizontal interconnect wire segments and diagonal interconnect wire segments.

Abstract: Some embodiments of the invention provide a method for propagating a first piecewise linear function (PLF), which is defined over a first state, to a second state, which is a line. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. For instance, in some embodiments, the space is a graph that includes points, lines, and surfaces. The method projects vectors from points on the first state that are locations of inflection points in the first PLF. At any intersection of the line and one of the vectors, the method computes a cost. The method also computes a cost at any endpoint of the line that does not intersect one of the vectors. Based on the computed costs, the method then specifies a second PLF that is defined over the second state.

Abstract: Some embodiments provide an LP method that identities routes. In some embodiments, this method is used by a router that defines routes for nets within a region of a design layout. Each net has a set of pins in the region. The method partitions the region into a set or sub-regions. For each particular net, the method identifies a set or route. Each route for a net traverses the sub-regions that contain the net's pins. Each route includes a set of route edge, and each route edge connects two sub-regions. Also, some of the identified routes have route edges that are at least partially diagonal. The method formulates a linear-programming (“LP”) problem based on the identified sets of routes for the nets. The method then solves the LP problem to identify one route for each net. In some embodiments, the formulated LP problem is an integer-linear-programming (“ILP”) problem, and solving the ILP problem returns integer solutions that specify one route for each net.

Abstract: The present invention introduces methods of creating floor plans and placements for non Manhattan integrated circuits with existing electronic design automation tools. To create a floor plan, an existing Manhattan based floor planning tool is used. The die size for the floor plan is reduced to take into account the improved wiring density of non Manhattan wiring. A non Manhattan global router is then used on the floor plan to create pin placements. The floor plan may create a floor plan having circuit modules with beveled corners to take advantage of diagonal wiring. To create a placement, an existing Manhattan based placer is first used to create an initial placement. The initial placement is then processed by a non Manhattan aware post processor. The post processor performs local optimizations on the initial placement to improve the placement for a non Manhattan routed integrated circuit.