Patents Represented by Attorney Stattler Johansen & Adeli LLP
  • Patent number: 7003406
    Abstract: Some embodiments of the invention provide a system for monitoring liquid consumption at one or more establishments. At each establishment, the system includes one or more spouts and a local computer. Each spout is mounted on a liquid container. Also, each spout generates data regarding the amount of liquid poured from the spout's container. The local computer at each establishment collects data generated by the spouts at the establishment. In some embodiments, a wireless network links the local computer and the spouts at each establishment. The system also includes an external computer that gathers the data collected by the local computers of the establishments monitored by the system. In some embodiments, the external computer is located outside of all the establishments, while in other embodiments this computer is located within one of the establishments. Some embodiments of the invention provide a free-pour spout.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: February 21, 2006
    Assignee: Capton, Inc.
    Inventor: Masoud Mike Mogadam
  • Patent number: 7000209
    Abstract: Some embodiments of the invention provide a method for propagating a first piecewise linear function (PLF), which is defined over a first state, to a second state, which is a surface. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. For instance, in some embodiments, the space is a graph that includes points, lines, and surfaces. The method projects vectors from points on the first state that are locations of inflection points in the first PLF. At each intersection of the boundary of the surface and one of the vectors, the method computes a cost. Based on the computed costs, the method specifying a second PLF that is defined over the second state.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: February 14, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 6996793
    Abstract: Geometric objects, such as polygons, are defined in a multi-dimensional data space, and are represented by data segments. “N” dimensional hierarchical trees, or “ng” trees, are generated to organize the data segments into “outside child nodes” and “inside child nodes” in accordance with a discriminator value. One of “n” sides of a polygon is selected as the discriminator value. To create the ng tree, data segments are designated as “outside child nodes” if a data segment is outside the plane defined by the discriminator value, and data segments are selected as “inside child nodes” if the data segment is inside the plane defined by the discriminator value. This process of partitioning data segments into inside child nodes and outside child nodes is repeated recursively through each level of the ng tree. Techniques to represent diagonal interconnect lines of regions defined in a multidimensional design layout of an integrated circuit are disclosed.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: February 7, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tom Kronmiller, Steven Teig
  • Patent number: 6996789
    Abstract: Some embodiments of the invention provide a method of searching for a path. The method identifies a set of source and target elements. It then performs a path search that iteratively identifying path expansions in order to identify a set of associated path expansions that connect the source and target elements. The method costs at least one expansion based on an exponential equation that has an exponent that includes a cost associated with the expansion.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: February 7, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Jonathan Frankle, Etienne Jacques
  • Patent number: 6990650
    Abstract: Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: January 24, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Asmus Hetzel
  • Patent number: 6988257
    Abstract: Some embodiments of the invention provide a method of defining a global route for a net in a region of a layout, where each net has a set of routable elements. The method partitions the region into several rectangular sub-regions. It then identifies a set of sub-regions that contain the routable elements of the net. Next, it defines a global route that connects the identified sub-regions, where the global route includes at least one non-Manhattan edge that crosses a boundary between two sub-regions at a non-vertex location.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: January 17, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Jonathan Frankle, Etienne Jacques, Andrew Caldwell
  • Patent number: 6988256
    Abstract: One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: January 17, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Joseph L. Ganley
  • Patent number: 6986117
    Abstract: Some embodiments provide a path-searching method. This method identifies two sets of states in a multi-state space, where at least some of the states have at least one dimension. The method performs a depth-first path search to identify a path between the two sets of states. During the path search, the method propagates a cost function that is defined over one state to another state.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: January 10, 2006
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 6980006
    Abstract: Envelope detector and method for determining whether the level of a differential input signal DPIN?DNIN is above a reference voltage VREF. The differential input signal is converted to a differential current IDP?IDN, the reference voltage is converted to a reference current IREF, the currents are compared to determine if |IDP?IDN| is greater than IREF, and a valid differential signal is indicated when |IDP?IDN| is greater than IREF.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: December 27, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Trung Nguyen, Hung Truong, Oanh Kim
  • Patent number: 6978432
    Abstract: Some embodiments of the invention provide a method for propagating a first piecewise linear function (PLF), which is defined over a first state, to a second state, which is a point. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. For instance, in some embodiments, the space is a graph that includes points, lines, and surfaces. The method projects vectors from points on the first state that are locations of inflection points in the first PLF. If the second state is between two projected vectors that emanate from a vector-emanating point on the first state, the method then computes a cost at the second state that equals the sum of the cost of the first PLF at the vector-emanating point and the distance between the vector-emanating point and the second state in the design layout.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: December 20, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 6976237
    Abstract: Some embodiments of the invention provide a method that computes an estimated distance between an external point and a set of points in the region. This method identifies a characteristic of the set of points. Based on the identified characteristic, the method then identifies a polygon that encloses the set of points. It then identifies a distance between the point and the polygon. Finally, it uses the identified distance to identify the estimated distance.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: December 13, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Jonathan Frankle
  • Patent number: 6973634
    Abstract: Some embodiments of the invention provide a region of an integrated-circuit (“IC”) layout that has a plurality of interconnect layers, where at least one particular layer has more than one preferred interconnect direction. In some of these embodiments, the region has several interconnect layers that have more than one preferred wiring direction each.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: December 6, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell, Etienne Jacques
  • Patent number: 6961914
    Abstract: The present invention introduces novel methods generating training data for machine learning models that will be used for extraction. Specifically, experimental design is employed to select a set of training points that provide the best information. In one embodiment, the training point set is created by creating a critical input spanning set, adding training points from critical regions in the input space, and adding training points from frequently encountered profile cases. The training point set then used to train a machine learning built model such as a neural network or support vector machine that will extract electrical characteristics.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: November 1, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Arindam Chatterjee
  • Patent number: 6959382
    Abstract: A digital signature service generates digital signatures for documents independent of the program used to transmit the documents. The digital signature service may operate as a Web server application, or as a client application on a user's computer. The digital signature service imports a certificate specific to a user. To digitally sign a document, the user identifies a document, and the digital signature service generates a single signature file that includes the user's certificate, the document, and the digital signature. With the signature file, the user may now store and/or transmit the file using any program while maintaining the integrity and authenticity capabilities associated with digital signatures. The digital signature service also permits multiple digital signatories to a single document. A secure document repository, implemented on a Web Site, is also disclosed.
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: October 25, 2005
    Assignee: Accela, Inc.
    Inventors: Tony F. Kinnis, Ho Wing Sit
  • Patent number: 6959304
    Abstract: The invention is directed towards method and apparatus for representing multidimensional data. Some embodiments of the invention provide a two-layered data structure to store multidimensional data tuples that are defined in a multidimensional data space. These embodiments initially divide the multidimensional data space into a number of data regions, and create a data structure to represent this division. For each data region, these embodiments then create a hierarchical data structure to store the data tuples within each region. In some of these embodiments, the multidimensional data tuples are spatial data tuples that represent spatial or geometric objects, such as points, lines, polygons, regions, surfaces, volumes, etc. For instance, some embodiments use the two-layered data structure of the invention to store data relating to geometric objects (such as rectangles) that represent interconnect lines of an IC in an IC design layout.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: October 25, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Tom Kronmiller, Andrew F. Siegel
  • Patent number: 6957408
    Abstract: Some embodiments of the invention provide a method of for routing nets within a region of an integrated circuit (“IC”) layout. The method selects a net in the IC layout region. It then identifies a topological route for the selected net. From the selected net's topological route, this method then generates a geometric route for the selected net.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: October 18, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell, Etienne Jacques
  • Patent number: 6957411
    Abstract: Some embodiments of the invention provide a method of routing nets in a region of an integrated-circuit (“IC”) layout. The method selects a net that has several routable elements. It then defines a route for the net. To define the route, the method uses a wiring model that specifies preferred non-Manhattan wiring directions. It also uses a manufacturing grid as the only grid for constraining the location of interconnect lines for connecting the net's routable elements.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: October 18, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell, Etienne Jacques
  • Patent number: 6957409
    Abstract: Some embodiments of the invention provide a method for identifying topological routes in a region of an integrated circuit (“IC”) design layout. The method receives a set of nets. Each net in the set has a set of routable elements in the IC design-layout region. For each net, the method then specifies a topological route that connects the net's routable elements. Each topological route is a route that represents a set of diffeomorphic geometric routes.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: October 18, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 6957410
    Abstract: Some embodiments provide a method of routing nets in a region of an integrated-circuit layout. This method initially identifies a characteristic of the region, and then selects a wiring model from a set of wiring models, based on the identified characteristic. Each wiring models specifies a set of routing directions. The method then routes the nets based on the selected wiring model.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: October 18, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset
  • Patent number: 6954115
    Abstract: A method for tuning a filter to a desired frequency using successive approximation. Elements of the filter are selected according to a control code used to vary the filter's oscillation frequency. The control code is set to the middle of the control code range and resulting oscillation frequency is compared to the desired frequency. If the control code needs to be increased, the control code is set to ¾ of the control code range. If the control code needs to be decreased, the control code is set to ¼ of the control code range. The method continues using successive approximation to determine the value of each bit of the control code. Thus, successive approximation is used to converge on the value of the control code that produces an oscillation frequency of the filter that is closest to the desired frequency (with a maximum error of 1 least significant bit).
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: October 11, 2005
    Assignee: RF Stream Corporation
    Inventor: Lance M. Wong