Abstract: A driver may be provided which controls the output slew rate a driver which includes within the driver a slew rate control circuit. Accordingly, a desired output slew rate can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a driver also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance.

Abstract: A switched converter uses two series connected complementary CMOS devices and has a square wave source for activating one CMOS device while deactivating the other; and a break before make circuit connected between the square wave source and said complementary CMOS devices to ensure that one device is substantially completely off before the other device turns on. The switched converter is programmable as to frequency, phase and duty cycle.

Abstract: An assembly including a slot in a peripheral device carrier and a tab in a housing for peripheral devices, the assembly providing a structure for retaining compatible peripheral devices in a computer system, and for preventing damage to connectors when an attempt is made to install an incompatible peripheral device. The peripheral devices include a first connector portion for electronically coupling the peripheral device to a processor in a computer system. The peripheral device is installed in the peripheral device carrier that includes a slotted side member and a front member. The slot may be located at one end of the side member, or the side member may be shortened or truncated to avoid the tab when the device carrier is inserted. The side member is attached to the front member thereby forming a portion of a frame for receiving the peripheral device. The housing includes a bay having a second connector portion and at least one opening for receiving the peripheral device carrier.

Abstract: A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a signal generation circuit which provides a differential current. The resolving circuit is coupled to a latching circuit. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal setup and hold times are inherently very small due to the high intrinsic bandwidth of the receiver. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 m Volt) voltage differences, reduced capacitive loading, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Abstract: A method for a driver may be provided which controls the output slew rate of a driver which includes within the driver an impedance control and a slew rate circuit. Accordingly, a desired output slew rate and a desired output impedance can be advantageously established and maintained over a wide range of variations in operating conditions, manufacturing processes and output voltage levels. Such a method also advantageously limits any crowbar current, thereby reducing the overall power consumption of the driver with little, if any, degradation of driver performance.

Abstract: The invention relates to a method for reporting errors during the operation of an Accelerated Graphics Port (AGP) device driver operating on an AGP chipset. The method includes providing an operating system with a persistent data file, determining whether an error has occurred during the operation of the AGP chipset device driver, writing an error code to the persistent data file, and returning to operation of the AGP chipset device driver.

Abstract: A lock and release mechanism is disclosed which includes an elongated bendable member which engages a lock tab such that when the lock tab is disengaged with the chassis an electronics module can be moved into a plurality of positions, including a service position, a closed position and a removal position. Such a mechanism advantageously provides latch and release functionality using a single part.

Abstract: The time required for executing a function over a network of computer systems in a high availability system is minimized. A list of computer systems is provided by a parent process. The list includes a plurality of computer systems upon which a first function is to be performed. The first function is received by the parent process. A plurality of child processes is sequentially created. Each of the child processes corresponds to one of the computer systems on the list. Each of the child processes executes in parallel with at least one other of the child processes. Each of the child processes remotely executes the first function on the computer system corresponding to the respective child process.

Abstract: A manufacturing system is disclosed which includes first and second control devices as well as a communication terminal which controls communication with the control devices. The communications terminal includes an interceptor module which receives information from the manufacturing device and provides this information to the first and second control devices.

Abstract: An apparatus and method is provided for installing and connecting one or more expansion boards in a computer system while the computer system is being manufactured as well as when a user upgrades or reconfigures the computer system. An expansion board bay for receiving the expansion board is located within the computer system, typically on a circuit board such as the motherboard. A connector module that is separate from the expansion board and the expansion board bay is positioned within the computer system. The connector module is positioned to provide easy external access to a contact portion of the connector module, thereby allowing a user to connect an external data signal line to the connector module. A connector cable operably connects the expansion board with the connector module to establish communication between the data processor and the external data line through the expansion board.

Abstract: The present invention provides a shared instruction cache for multiple processors. In one embodiment, an apparatus for a microprocessor includes a shared instruction cache for a first processor and a second processor, and a first register index base for the first processor and a second register index base for the second processor. The apparatus also includes a first memory address base for the first processor and a second memory address base for the second processor. This embodiment allows for segmentation of register files and main memory based on which processor is executing a particular instruction (e.g., an instruction that involves a register access and a memory access).

Abstract: A method for configuring an Accelerated Graphics Port (AGP) chipset having an AGP chipset cache. The method includes providing an operating system with a persistent data file, the persistent data file storing cache configuration parameter information for configuring the AGP chipset cache, loading the cache configuration parameter information from the persistent data file upon execution of an AGP chipset driver, and configuring the AGP chipset cache based upon the cache configuration parameter information.

Abstract: By monitoring the output voltage of a mass flow controller (MFC) there is no way to detect when a MFC is starting to degrade (or beginning to fail) as long as the MFC output voltage is driven to match the MFC setpoint voltage. Only when the MFC actually fails, and the MFC output voltage is unable to be driven to match the MFC setpoint voltage, is the failure detectable. A predictive failure monitoring system for a mass flow controller (MFC) is disclosed which monitors the “valve voltage” of the MFC as well as the MFC output voltage. By knowing the normal relationship between the MFC setpoint voltage and the respective valve voltage, then degradation or other changes may be noticed before the MFC actually fails, and importantly, before production material is ruined by the failing MFC. Such a real-time monitoring capability may be transparently implemented as an add-on module between the MFC and the system controller for the MFC.

Abstract: A battery charging apparatus, computer system and method provide current from a single power line to charge either a first battery or multiple batteries in an independent mode or a simultaneous mode. The apparatus includes an AC-to-DC adapter, the power line, and a battery charging control system that measures the charge of the individual batteries and compares the measured charge. If the charging system detects a difference in charge between the batteries, the lowest or the lower charged batteries are charged until the charging system detects no difference in charge, and then resumes simultaneous charging. The battery charging control system also includes a comparator circuit that determines whether to enable charging in the independent mode or the simultaneous mode based on input from a user or input from a computer system. The computer system includes a processor, a memory, a bus, a power line, and a battery charging apparatus coupled to the power line.

Abstract: The stabilizing apparatus of the present invention has the advantages of allowing the computer system tower units to be positioned in close proximity with respect to each other while providing stability for a single or multiple tower units. The present invention provides a stabilizing apparatus for a computer system having one or more tower units with a generally narrow width base with respect to the depth and height of each tower unit. At least one pedestal spans the base of the tower unit in a direction transverse to the depth of the tower unit. The pedestal of the present invention is a single bar having two ends which extend outwardly from opposite sides of the tower unit for preventing the tower unit from overturning. Alternatively, the ends are also angled downwardly for raising the base of the tower unit. Screws are used, for instance, to attach the pedestal to the tower unit.

Abstract: A delay-locked loop includes a phase detection circuit, a charge pump circuit and a phase shift circuit. The phase detection circuit is coupled to receive a first signal and a second signal. The phase detection circuit generates a phase-error output signal indicative of whether the first signal is ahead of or behind the second signal in phase responsive to receiving the first and second signals. The charge pump circuit is coupled to receive a phase-error signal derived from the phase-error output signal. The charge pump circuit generates a plurality of control output signals. Each of the control output signals are based upon the phase-error signal and by at least one signal derived from one other of the control output signals. The phase shift circuit is coupled to receive a plurality of control input signals and a plurality of periodic input signals. The control input signals are derived from the control output signals. Each of the periodic input signals have a different phase.

Abstract: A camera is targeted using voice recognition analysis. Audio information is received by a talker identification (TID) module from a microphone. The TID module automatically performs a voice recognition analysis on the audio information to uniquely identify which of a plurality of talkers is talking. The camera is automatically controlled to target a camera preset location corresponding to the talker identified to be talking.

Abstract: An external universal battery charging apparatus which can include external universal battery charger circuitry having at least one universal battery charger circuitry input and at least one universal battery charger circuitry output. The universal battery charger circuitry output can include at least one battery charger output, which itself can include at least one universal battery connector and at least one universal battery charger cable. The at least one universal battery charger circuitry output can include at least one adapter pass through output, which itself can include at least one connector adapted to operably connect to an electronic device. The external universal battery charger circuitry can include at least one battery recognition and parameter adjustment circuit, battery current parameter adjustment circuit, charged voltage parameter adjustment circuit, and maximum power draw parameter adjustment circuit.

Abstract: A superscalar complex instruction set computer (“CISC”) processor having a reduced instruction set computer (“RISC”) superscalar core includes an instruction cache which identifies and marks raw x86 instruction start and end points and encodes “pre-decode” information, a byte queue which is a queue of aligned instruction and pre-decode information of the “predicted executed” state, and an instruction decoder which generates type, opcode, and operand pointer values for RISC-like operations (ROPs) based on the aligned pre-decoded x86 instructions in the byte queue and determines the number of possible x86 instruction dispatch for shifting the byte que. The instruction decoder includes in each dispatch position a logic conversion path, a memory conversion path, and a common conversion path for converting CISC instructions to ROPs.

Abstract: An apparatus for accessing locked-down flash memory in a computer system that utilizes a general purpose input/output port coupled to the flash memory, and includes program instructions that generate a reset signal, output the reset signal to the general purpose input/output port, sense the reset signal, unlock the flash memory to allow write access to the flash memory, update the flash memory, and lock the flash memory to locked down mode. The present invention allows flash memory to be updated during normal operation of the computer system.