Abstract: A method, system and computer program product for adaptive messaging in a computer network having a client machine and at least one server. Typically, the client machine is located behind a firewall. According to the invention, a communication from the server to the client may be “repackaged” in an e-mail message in the event a point-to-point connection between the server and the client cannot be established due to the firewall or some other network constraint. The client typically communicates with the server by the point-to-point connection. The technique is especially useful in an automated diagnostic method wherein users of client machines interact with a diagnostic system located at a server.

Abstract: A power supply filter capable of functioning with low power supply voltages includes a resistor-capacitor circuit coupled to a power supply line and a transistor for providing power to a target circuit, such as a phase-locked loop circuit, coupled between the resistor-capacitor circuit and the power supply line. The resistor-capacitor circuit is coupled to a charge pump controller to keep the transistor in a saturation state. The charge pump controller receives at least one clock signal that is coupled to at least one capacitive circuit. The at least one capacitive circuit includes at least two capacitors in series with a biased middle node located between the at least two capacitors in order to provide immunity to time dependent dielectric breakdown, the middle node coupled to approximately half the power supply line.

Abstract: A chassis retaining system for securing a chassis supporting electronic equipment such as a computer system to a rack. The chassis retaining system includes a handle and a securing device with a retaining surface. The securing device is coupled to the handle, and the retaining surface is movable with respect to the handle. The chassis retaining system further includes a user interface device coupled to the handle and to the securing device. The user interface device is movable with respect to the handle. The user interface device is engageable by a user to move the retaining surface from a first position with respect to the handle wherein a surface of the electronics rack in which a chassis is mounted retains the retaining surface, to a second position wherein the surface of the electronics rack does not retain the retaining surface.

Abstract: A switching flyback regulator circuit for providing a plurality of regulated DC voltage power supplies. The flyback regulator circuit includes a primary inductive element coupled in series with a first switch to turn charging current flow through the primary inductive element ON and OFF. A first secondary inductive element having a first end coupled to supply a first power source. A second secondary inductive element has a first end coupled to produce the second power source, and a second end coupled to a second switch to turn current flow through the second secondary inductive element ON and OFF. The first secondary inductive element and the second secondary inductive element are magnetically coupled to the primary inductive element.

Abstract: A personal computer system is disclosed which is compatible with application programs and operating system software. The personal computer system includes a microprocessor electrically coupled to a data bus, non-volatile memory electrically coupled to the data bus, volatile memory electrically responsive to the data bus, a memory controller electrically coupled to the microprocessor, the volatile memory and the non-volatile memory, and a direct access storage device electrically responsive to the data bus. The non-volatile memory stores a first portion of operating system microcode and the volatile memory includes a volatile operating system portion intended for use by the first portion of the operating system microcode. The memory controller regulates communications between the volatile memory, the non-volatile memory and the high speed microprocessor. The direct access storage device stores a second portion of operating system microcode which includes a plurality of modules.

Abstract: A portable computer system with a special connector, on the motherboard, into which a field-installable boot card can be inserted. The special motherboard connector is wired so that the operator, by setting connections on the field-installable boot card, can bypass the boot memory on the motherboard and force the computer to boot from the memory on the boot card. This permits a technician, in the field, to temporarily override the internal nonvolatile memory which holds the basic system software. This permits recovery of a system in which the basic system software has been corrupted. Preferably the motherboard boot memory is a flash EPROM, and can be rewritten, by setting appropriate jumpers on the boot card, after the computer has booted from the boot card. The motherboard connector is preferably located on the motherboard, and is accessible through a removable cover. This connector can also preferably be used for temporary attachment of a diagnostic display card.

Abstract: A personal computer system which is compatible with application programs and operating system software is disclosed. The personal computer system includes a microprocessor electrically coupled to a data bus, non-volatile memory electrically coupled to the data bus, volatile memory electrically responsive to the data bus, a memory controller electrically coupled to the microprocessor, the volatile memory and the non-volatile memory, and, a direct access storage device electrically responsive to the data bus. The non-volatile memory stores a first portion of operating system microcode and request information which indicates whether a second portion of operating system microcode is required by the personal computer system. The volatile memory includes a volatile operating system portion intended for use by the first portion of the operating system microcode. The memory controller regulates communications between the volatile memory, the non-volatile memory and the high speed microprocessor.

Abstract: An information handling apparatus for transferring and composing image signals including a plurality of media sources configured to provide a corresponding plurality of image signals, a media bus connected to the media sources, and a media control module coupled to the media bus. The media bus allows selective access for the plurality of image signals. The selective access enables composition of the independent image signals in response to control information. The media control module receives a composed image signal from the media bus and provides the composed image signal to a display device.

Abstract: A multimedia solution is presented which allows a multimedia architecture to be implemented on an existing computer system. According to the invention, an expansion unit which incorporates a multimedia architecture is provided. The expansion unit is connected to an existing computer system via an expansion slot of an I/O bus of the existing computer as well as via a display device output terminal of the computer. The expansion unit is also connected to a display device. Accordingly, the expansion unit controls the presentation which is provided on the display device.

Abstract: A method and system for permitting simultaneous communication between a data processing system and input pointing devices of multiple types. During the initialization of an operating system, each input pointing device which is coupled to a data processing system is automatically identified. Thereafter, in response to each input from any one of the identified input pointing devices, a particular software routine is automatically selected, thus permitting each identified input pointing device to communicate with the data processing system.

Abstract: A computer system is provided comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to a plurality of input/output devices by an input/output bus. The bus interface unit is able to sense when said one of said input/output devices has completed a read or write operation over said input/output bus, and includes a buffer circuit wherein read and write data transferred between the system bus and the input/output bus via the bus interface unit is temporarily stored during the transfer. Arbitration control logic resides in said bus interface unit and interacts with a central arbitration controller which resides on the system bus.

Abstract: A computer system which includes a synchronous digital, multibit system bus having a clock path, a master speed indicator path and a slave speed indicator path, a bus control circuit which provides first and second clocks to the clock path of the bus, the second clock having a different frequency than the first clock, and a master circuit and a slave circuit connected to the system bus. The master circuit includes master speed indication circuitry which provides a master speed indicator indicating the operating speed of the master circuit to the master speed indicator path. The slave circuit includes slave speed indication circuitry which provides a slave speed indicator indicating the operating speed of the slave circuit to the slave speed indicator path. The bus controller provides the second clock when the master speed indicator and the slave speed indicator indicate that the master circuit and the slave circuit both may function at the different frequency of the second clock.

Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to an input/output device by an input/output bus. The bus interface unit includes translation logic for temporarily storing, in response to a predetermined set of operating conditions, data transferred between the system bus and the input/output bus through the bus interface unit.

Abstract: An information handling apparatus for transferring and composing image signals for display. The apparatus includes a bus adapted to allow selective access for multiple independent image signals generated by respective independent image sources. The selective access enables composition of the independent image signals in response to control information; the composition enables real time display of a composed image signal.

Abstract: In a computer system having both peripherals having their own DMA channel arbiter and peripherals having no arbiter, a separate arbitration unit, controlled directly by the CPU, is provided to arbitrate on behalf of peripherals having no arbiter. The CPU can thus freely assign different arbitration levels to such peripherals, and can instruct the arbitration unit to simultaneously arbitrate on different arbitration levels or for two or more DMA channels.

Abstract: An arbiter with first and second CPU timers is provided which advantageously allows measuring and controlling CPU bus ownership intervals via the arbiter. The first CPU timer, a running timer, specifies the total interval that the CPU is allocated the bus. The second time, an idle timer, specifies an interval which the CPU may own the bus without performing an operation. The arbiter uses these two timers to dynamically adjust and control CPU bus ownership.

Abstract: An improved I/O channel check and parity check detector includes two similar detection paths each of which includes a check detector, a glitch reject circuit, and a read back register. A memory parity error causes a bit to be set in the read back register. An I/O channel check sets another bit in a read back register provided a memory parity error has not been signalled. If such signal occurs, the channel check is rejected. The read back bits are read through a port allowing the system to determine the source of error.

Abstract: An information handling apparatus for transferring and composing image signals for display including a bus interface circuit adapted to allow selective access to a bus of an independent image signal generated by an independent image source. The selective access enables composition of the independent image signal in response to control information; the composition enables real time display of a composed image signal.

Abstract: A personal computer system according to the present invention comprises a system processor, a random access memory, a read only memory, and at least one direct access storage device. A direct access storage device controller coupled between the system processor and direct access storage device includes a protection mechanism for protecting a region of the storage device. The protected region of the storage device includes a master boot record, a BIOS image and a system reference diskette image. The BIOS image includes a section known as Power on Self Test (POST). POST is used to test and initialize a system. Upon detecting any configuration error, system utilities from the system reference diskette image, such as set configuration programs, diagnostic programs and utility programs can be automatically activated from the direct access storage device.

Abstract: An apparatus and method for loading BIOS stored on a direct access storage device into a personal computer system. The personal computer system comprises a system processor, a system planar, a random access main memory, a read only memory, and at least one direct access storage device. The first portion of BIOS initializes the system and the direct access storage device to read in a master boot record into the system from the direct access storage device. The master boot record includes a data segment and an executable code segment. The first BIOS portion vectors the system processor to execute the executable code segment of the master boot record. The executable code segment loads in the remaining BIOS portion from the direct access storage device into random access memory.