Abstract: A semiconductor memory is provided wherein two bits of binary information are stored simultaneously in a ferroelectric capacitor by utilizing the positive and negative polarization states of the ferroelectric capacitor for storing a first of the two bits of binary information and by utilizing the capacitive characteristic of the ferroelectric capacitor to simultaneously store a second of the two bits of binary information without altering the polarization of the ferroelectric capacitor. When reading information from the ferroelectric capacitor, the second of the two bits of information is read out first and transferred to a buffer cell, then the first of the two bits of binary information is read and re-written, as desired, and the second of the two bits of information is returned from the buffer cell to the ferroelectric capacitor.

Abstract: A power up detection circuit is provided which includes a power supply terminal, an output terminal, an impedance device coupling the output terminal to the power supply terminal and a latch including a first inverter having a first device connected between the output terminal and a point of reference potential and a second device connected between the output terminal and the power supply terminal, the devices are designed so that subthreshold current passing through the first device is greater than the effective subthreshold current passing through the impedance device and the second device, and a second inverter including third and fourth devices which are designed so that a smaller subthreshold current passes through the third device than the subthreshold current passing through the fourth device. The power up circuit may further include a capacitor connected between the power supply terminal and gate electrodes of the first and second devices.

Abstract: An improved short channel field effect transistor is provided which includes a semiconductor substrate having a given type dopant with source and drain electrodes, one of the electrodes having a diffusion of the type of dopant opposite to that of the given type dopant, a channel disposed between the source and drain electrodes, a region having the same type dopant as that of the substrate and aligned with the diffusion at the diffusion-channel interface, the region having sufficient dopant to prevent penetration of the depletion region generated by the diffusion into the substrate or at least to significantly limit the electric field which results from the junction between the diffusion and the substrate and an electrically conductive contact made with the diffusion, which may be, e.g., connected to a substantially constant bias or supply voltage source.

Abstract: A micro electrostatic cooling fan arrangement is provided which includes a heat source having a planar surface, a stator attached to the heat source, an axle attached to the heat source and spaced from the stator, a rotary element including a hub having an aperture therein and a fan blade, the axle passing through the aperture of the hub and the fan blade having a major surface thereof disposed at an angle with respect to the surface of the heat source and attached to the hub at one end, with the other end of the fan blade being adjacent to but spaced from the stator and a voltage source applied to the stator having sufficient voltage to charge the fan blade.

Abstract: A redundancy system formed on a semiconductor chip is provided which includes circuits for testing a memory array to locate a faulty element therein, a register for storing an address of the faulty element and electrical fuses blown in response to binary digits of the address stored in the register upon application of an enable signal from a single input to the semiconductor chip. The enable signal passes through logic circuits on the chip such that the fuses cannot be programmed or blown unless the enable signal is present. An address decoder coupled to outputs from the fuses substitutes a redundant element for the faulty element.

Abstract: A micro electrostatic cooling fan arrangement is provided which includes a heat source having a planar surface, a stator attached to the heat source, an axle attached to the heat source and spaced from the stator, a rotary element including a hub having an aperture therein and a fan blade, the axle passing through the aperture of the hub and the fan blade having a major surface thereof disposed at an angle with respect to the surface of the heat source and attached to the hub at one end, with the other end of the fan blade being adjacent to but spaced from the stator and a voltage source applied to the stator having sufficient voltage to charge the fan blade.

Abstract: A signal margin testing system is provided for a memory having a word line voltage boosting circuit which uses a test mode decode circuit to selectively disable the word line boosting circuit and then read out data from storage cells in the memory.

Abstract: An improved contactless temperature measurement system is provided which includes a workpiece, a chamber containing the workpiece with the walls thereof being substantially transmissive to radiation at wavelengths other than a given wavelength and substantially reflective at the given wavelength to remove the dependence of the apparent or measured temperature on the workpiece emissivity variations or fluctuations.

Abstract: A single to fully differential converter for fully differential switched capacitor circuits is provided which can be incorporated into a switched capacitor integrator architecture performing both conversion and integrating functions without affecting the performance of the fully differential integrator.

Abstract: In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation, e.g., processing/logging error data, prior to a processor start. One or more reset areas are defined which are initialized/reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause, e.g., power-on, for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.

Abstract: A CMOS off-chip driver circuit is provided which includes a P-channel pull up transistor and an N-channel pull down transistor serially arranged between a first voltage source having a supply voltage of a given magnitude and ground with the common point between the transistors forming an output terminal to which is connected a circuit including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. A first P-channel field effect transistor is connected between the output terminal and the gate electrode of the pull up transistor.

Abstract: A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.

Abstract: A test selection system is provided which includes a semiconductor substrate having a pin connected thereto and an integrated circuit disposed on the substrate and connected to the pin having an operating voltage within a given voltage range. A latch conditioning circuit having an input responsive to a voltage of a given magnitude has an output connected to a latch, and a voltage control circuit operable at a voltage without the given voltage range selectively applies a control voltage of the given magnitude to the input of the latch conditioning circuit. A voltage without the given voltage range is applied to the pin during a first interval of time to produce the control voltage for establishing a test mode and a voltage within the given voltage range is applied to the pin during a second interval of time to establish a normal operating mode for the integrated circuit.

Abstract: A very small memory cell utilizing only two squares at a major surface is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, a storage capacitor having a storage node disposed within a given sidewall of the trench, a switching device coupled to the storage capacitor and having an elongated current carrying element disposed within the given sidewall with its longitudinal direction arranged parallel to that of the longitudinal axis of the trench and a control element disposed on the sidewall of the trench between the storage capacitor and the elongated current carrying element, and an electrically conductive line disposed on the major surface of the semiconductor substrate in a direction orthogonal to the longitudinal axis of the trench and in contact with the control element of the switching device.

Abstract: Low power addressing systems are provided which include a given number of memory segments, each having word and bit/sense lines, a given number of decoders coupled to the given number of memory segments for selecting one word line in each of the memory segments, a first plurality of transmission gate systems, each having first and second transmission gates, with each of the gates being coupled to a different one of the decoders, a second decoder having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems, first control circuits for selectively activating the first and second gates in each of the first plurality of transmission gate systems, a second given number of decoders coupled to the given number of memory segments for selecting one bit/sense line in each of the memory segments, a second plurality of transmission gate systems, each having first and second transmission gates, with each of the gates of the second plurality of transmission ga

Abstract: To remove small particles from surfaces of solid bodies at least one laser pulse of high power density (excimer laser) is directed onto the surface. The method is particularly suited to clean Si-masks used in electron-beam lithographic devices. An arrangement for in-situ-cleaning of masks in accordance to this method is integrated in such an electron-beam lithographic device.

Abstract: A voltage clamping circuit is provided which includes first condutivity type and second conductivity type transistors serially arranged between first and second reference potential terminals. First control means including a first inverter are connected from the common point between the transistors to a control electrode of the first conductivity type transistor, and second control means including a second inverter are connected from the common point between the two transistors to a control electrode of the second conductivity type transistor, with the first and second inverters having different switching points.

Abstract: A driver circuit is provided which includes an output stage having first and second transistors and an output terminal, the first transistor being of a first type conductivity is coupled from the output terminal to a first point of reference potential and the second transistor being of a second type conductivity is coupled from the output terminal to a second point of reference potential. A first voltage divider includes transistors of the first type conductivity and a second voltage divider includes transistors of the second type conductivity. A second transistor of the first type conductivity is connected between the first point of reference potential and a control electrode of the first transistor of the first type conductivity and a second transistor of the second type conductivity is connected between the second point of reference potential and a control electrode of the first transistor of the second type conductivity.

Abstract: An improved voltage regulator system is provided which includes a differential amplifier, an output transistor having a control electrode coupled to an output of the differential amplifier and a current carrying electrode fed back to an input of the amplifier, an input control transistor having a first current carrying electrode connected to the control electrode of the output transistor and a second current carrying electrode connected to a point of fixed potential and means for selectively applying a control signal to a control electrode of the input control transistor.

Abstract: A circuit is provided, of the multiplexer type, which includes pass gates having first and second P-channel field effect transistors and first and second N-channel field effect transistors, a first data signal is applied to first current-carrying electrodes of the first P-channel and first N-channel transistors with a second data signal applied to first current-carrying electrodes of the second P-channel and second N-channel transistors, second current-carrying electrodes of the first and second P-channel transistors being connected together and second current-carrying electrodes of the first and second N-channel transistors being connected together and coupled to the second current-carrying electrodes of the first and second P-channel transistors. A true control pulse is applied to control electrodes of the first N-channel transistor and of the second P-channel transistor and a complemented control pulse, i.e.