Abstract: This invention provides improved non-volatile semiconductor memories which form non-inverting signals and which include a one device dynamic volatile memory circuit having a storage capacitor which includes a conductive plate, a charged floating gate and an inversion layer in a semiconductor substrate together with a non-volatile device including the floating gate, a control electrode and a voltage divider having first and second serially-connected capacitors, with the floating gate being disposed at the common point between the first and second capacitors. The plate of the storage capacitor is connected to a reference voltage source. The control electrode is capacitively coupled to the floating gate through the first capacitor which includes a charge or electron injector structure. The capacitance of the first capacitor has a value, preferably, substantially less than that of the second capacitor which is formed between the floating gate and the semiconductor substrate.

Abstract: A system is provided in which two load devices connected to a latch are individually controlled and connected to a common input/output line. A bit/sense line is connected to each of two nodes on the latch. By providing two such latches each with bit/sense lines and two individually controlled load devices connected to the common input/output line, two cells of a word line may be sensed simultaneously.

Abstract: A memory system is provided wherein extended injection-limited programming techniques attain a substantially uniform programming behavior from an ensemble of fabricated devices or cells to provide the maximum obtainable voltage threshold shift within a minimum time period. In order to produce these desired results, a floating gate of a device is charged by applying to the control gate of the device a first voltage during a portion of this time period which produces an accelerating field in a dielectric layer disposed adjacent to the floating gate and then applying to the control gate during the remaining portion of this time period a second voltage of greater magnitude than that of the first voltage prior to or when the accumulation of charge on the floating gate causes a retarding field to be established in the dielectric layer.

Abstract: A self-starting, negative voltage band gap regulator is provided, which includes a transconductance amplifier having first and second transistors and a resistive network, a current mirror circuit coupled to the amplifier and a negative feedback circuit connected from the collector of one of the transistors to the emitters of the transistors through said resistive network. First and second matched impedances, such as diodes, are included in the current mirror circuit and in the feedback circuit, respectively. The output voltage is taken from the feedback circuit.

Abstract: An improved method of fabricating a stable high dielectric constant and low leakage dielectric material includes oxidizing at a temperature of about 400.degree. C. or higher a layer of a transition metal-silicon alloy having 40% to 90% transition metal by atomic weight to produce a silicate or homogeneous mixture. The mixture includes an oxide of the transition metal and silicon dioxide. The alloy may be deposited on, e.g., a semiconductor or an electrically conductive layer that is oxidation resistant, and the thickness of the mixture or oxidized alloy should be within the range of 5 to 50 nanometers. By depositing an electrically conductive layer on the homogeneous mixture, a capacitor having a high dielectric, low leakage dielectric medium is provided.

Abstract: This invention provides a system for selectively driving one word line of a plurality of word lines in a memory array which includes a first highly capacitive common line connected to a plurality of driver circuits, each of which has connected to its output a respective word line and each of which includes a transistor having a capacitive junction connected to the common line. Means are provided for charging the common line and for rapidly discharging the common line through a selected driver circuit to its associated word line. Additionally, a second highly capacitive common line is connected to a point of reference potential through a resistor, with each of the driver circuits being connected between said first and second common lines.

Abstract: A switchable bipolar structure, suitable for use in a programmable read only memory, is provided which includes a rectifying contact disposed on a N type semiconductor substrate with a P type diffusion region formed in the substrate spaced within a minority carrier diffusion length from the rectifying contact. A conductive filament is selectively formed between the rectifying contact and the P type diffusion region by applying a reverse bias voltage between the rectifying contact and the N type substrate having a magnitude sufficiently large so as to form a liquid alloy having a front moving in the direction of current flow. By maintaining the P type diffusion region at a positive voltage with respect to the voltage on the rectifying contact, the liquid alloy front moves from the rectifying contact to the P type diffusion region forming a conductive filament or segment therebetween.

Abstract: A memory system is provided having an array of cells, each of which may include first and second cross-coupled inverting NPN transistors and first and second PNP transistors for injecting charge into the first and second inverting transistors. A first bit/sense line of a bit/sense line pair is connected to the emitter of the first inverting transistor and a second bit/sense line of the pair is connected to the emitter of the second inverting transistor and a common word line is connected to the emitters of the first and second charge injecting transistors. To read a selected cell, all cells of the array are discharged through the word lines, the pair of bit/sense lines connected to the selected cell are electrically floated or isolated and the word line connected to the selected cell is energized by a word driver. The signal developed in the bit/sense lines connected to the selected cell is detected while the word line connected to the selected cell is being energized by the word driver.

Abstract: A method is provided for making complementary field effect transistors in a semiconductor layer having a first portion including an N type transistor with a channel region defined by N+ source and drain regions and having a second portion including a P type transistor with a channel region defined by P+ source and drain regions. An insulating layer is disposed over the first and second portions with thin insulating films formed over the channel regions.

Abstract: This invention provides improved non-volatile semiconductor memories which include a volatile latch circuit having a data node and first and second cross-coupled transistors, at least one of the transistors has first and second control gates, a floating gate and an enhanced conduction insulator or dual electron injector structure disposed between the first control gate and the floating gate. The second control gate is connected to the storage node. A control voltage source is connected to the first control gate for transferring charge between the enhanced conduction insulator or dual electron injector structure and the data node.

Abstract: An improved method of fabricating a silicide structure includes depositing a metal, e.g., molybdenum or tungsten, directly onto a thin insulating layer of silicon dioxide and/or silicon nitride formed on a semiconductor substrate, co-depositing the metal and silicon onto the metal layer and then depositing silicon onto the co-deposited metal-silicon layer. This structure is annealed at a temperature sufficient to form a metal silicide between the thin insulating layer and the layer of silicon. The silicon layer serves as a source of silicon for the metal layer which is consumed during the annealing step to form, along with the co-deposited metal-silicon layer, a relatively thick metal silicide layer directly on the thin silicon dioxide layer. A sufficiently thick silicon layer is initially provided on the co-deposited metal-silicon layer so that a portion of the initial silicon layer remains after the annealing step has been completed.

Abstract: A word line selection circuit includes a conventional Schottky diode decoder and a driver transistor which is connected to a word line. A word line is selected when the transistor is conductive and all associated diodes of the decoder are off. The base current of the driver transistor is defined by a control transistor whose conductivity is opposite to that of the driver transistor and which applies the selection current to the base of the driver transistor. A regulating transistor forms a current mirror with the control transistor to regulate the selection current. A compensation circuit associated with the regulating transistor modulates the collector current of the regulating transistor as a function of the driver transistor factor.

Abstract: A saturation-limited bipolar transistor device or circuit and a method of making same are provided which includes a merged NPN transistor and a PNP transistor structure formed so as to produce denser cells or circuits. A simple process is used to form the structure which includes a double diffused technique for making the PNP transistor. The PNP transistor has a double diffused emitter-base arrangement wherein the emitter is asymmetrically positioned with respect to the base so as to also serve as a contact for the base of the NPN transistor. The PNP transistor limits the input current by bypassing excess current to a silicon semiconductor substrate or chip. The structure includes an N type epitaxial layer formed on an N type subcollector with a P type region provided near the surface of the epitaxial layer. The epitaxial layer serves as the NPN collector and as the PNP base contact region.

Abstract: This invention provides improved non-volatile semiconductor memories which include a volatile circuit coupled to a non-volatile device having a floating gate and first and second control gates capacitively coupled to the floating gate with a charge injector structure disposed between the floating gate and one of the two control gates. The volatile circuit may be a dynamic one-device cell or a static cell such as a conventional flip-flop or latch cell.

Abstract: The circuit rapidly charges and discharges a load capacitor by sensing the direction of transients at an internal node of the circuit which is selectively isolated from a capacitive output node to produce significant load current during upward transients. In an embodiment of the invention, the circuit includes a driver device and first, second and third field effect transistors. The first transistor is connected between a voltage supply terminal and the driver device forming an internal node between the first transistor and the driver device and acts as a current source pulling up the internal node. The second transistor is connected between the internal node and an output node and is arranged to selectively isolate the internal node from the output node, with isolation increasing during a positive transient to allow maximum drive to the third transistor connected between the voltage supply terminal and the output node to produce increased output current.

Abstract: An electrically alterable double dense memory is provided which includes a field effect transistor having first and second spaced apart diffusion regions of a first conductivity defining a channel region at the surface of a semiconductor substrate having a second conductivity. First and second floating gates are disposed over the first and second diffusion regions, respectively, and each extends over an end of the channel region. First and second dual charge injector structures or enhanced conduction insulators are disposed between the first and second floating gates and a common control gate of the transistor. A word line is connected to the control gate and first and second bit lines are connected to the first and second diffusion regions. By applying appropriate pulses to the word and bit lines, a selected floating gate can be charged to alter the conductivity of the end of the channel region associated with the selected floating gate and then discharged at will.

Abstract: A driver circuit charges a capacitive load to a voltage substantially equal to the voltage or potential of the power supply of the circuit by first charging the capacitive load with current flowing through a drive transistor under the control of the power supply potential and, thereafter, at a predetermined time charging the capacitive load under the control of a precharged bootstrap capacitor. The driver circuit includes a transistor, acting as a pull-up device, connected between the power supply and the capacitive load and a series circuit including a charge source and switching means connected between the capacitive load and a control gate of the transistor. The switching means is coupled to the capacitive load so as to be responsive to the voltage at the load for directing charge from the charge source into the pull-up transistor at a predetermined time to raise the voltage at the capacitive load to substantially the potential of the power supply.

Abstract: This invention provides an improved electrically alterable read only memory system which includes a semiconductor substrate having a diffusion region therein defining one end of a channel region, a control plate, a floating plate separated from the channel region by a thin dielectric layer and disposed between the control plate and the channel region and means for transferring charge to and from the floating plate. A control gate is coupled to the channel region and is located between the diffusion region and the floating plate. The control gate may be connected to a word line and the diffusion region may be connected to a hit/sense line. The channel region is controlled by the word line and the presence or absence of charge on the floating plate. Thus, information may be read from a cell of the memory by detecting the presence or absence of charge stored in the inversion capacitor under the floating plate.

Abstract: This invention provides improved non-volatile semiconductor memories which include a one device dynamic volatile memory circuit having a storage capacitor with a plate and a storage node coupled to a non-volatile device having a floating gate, a control gate and a voltage divider having first and second serially-connected capacitors, with the floating gate being disposed at the common point between the first and second capacitors. The plate of the storage capacitor is connected to a reference voltage source. The control gate is preferably capacitively coupled to the floating gate through the first capacitor which includesa dual charge or electron injector structure. The capacitance of the first capacitor has a value substantially less than that of the second capacitor.

Abstract: An integrated delay circuit has been provided which comprises a bipolar transistor and more particularly a PNP transistor having a diffusion capacitor of a given storage capacity as a time delay element and means including a switching device coupled to the junction capacitor for controlling current flow through the transistor. The switching device, which is preferably a Schottky diode, includes a capacitor having a charge storage capacity less than, and preferably substantially less than, that of the transistor. In the closed condition of the switching device a constant or steady current is sustained through the transistor and in the opened condition of the switching device the current through the transistor decreases exponentially. By coupling the output current from the transistor to a current level detector or comparator controlled delay times of substantial duration are produced in bipolar circuit technology.