Abstract: A digital to analog converter for converting an N-bit digital word into its analog representation including means for splitting the N bits into n sections of N/n bits each. For instance a 12-bit word is split into an odd section and an even section which are processed independently and in parallel. This results in two partial results, V.sub.i and V.sub.p, respectively, representative of the odd and even bit sections. The last step of the conversion is the action of the two partial results V.sub.i and V.sub.p to provide the analog representation of the 12-bit word. Few operators are required to process each section because each bit is converted sequentially. This provides a low cost, compact and simple converter, moreover, since few operators are required, it may be advantageous to use high precision operators as disclosed.

Abstract: Memory comprising a matrix of conventional Harper pnp cells and peripheral circuits which allows it to be used either as a random access memory or as an associative memory. In addition to the read/write circuits which are inhibited in search mode, it comprises search mode control circuits 7-1 to 7-m to provide the memory cells with a search argument DI-1 to DI-m and search circuits 11-1 to 11-n connected to the word lines for detecting the match or mismatch conditions. A search restore circuit 15 common to all word lines WL is used to restore the work lines to a quiescent voltage once the search operation is completed. Circuits 7 and 11 are inhibited in read/write mode.

Abstract: A method of automatically forming identically positioned alignment marks on the front side and the back side of a silicon wafer especially prepared for use in silicon micromechanical technology. The front side and the back side of the silicon wafer are coated with an insulating layer. High-energy heavy ions are directed onto the front side insulating layer. The heavy ions penetrate the front side insulating layer, the wafer, and the back side insulating layer, thus forming single disturbed crystal lattice nuclear tracks in both insulating layers, with the wafer remaining undisturbed.The nuclear tracks in both insulating layers are etched so that corresponding identically positioned pores are opened. These pores are used as alignment marks for individual further method steps.

Abstract: A power supply adapter system is provided which includes a voltage supply source terminal, an output terminal, first and second switches, the first switch being disposed between the voltage supply source terminal and the output terminal, voltage conversion means serially connected with the second switch and disposed between the voltage supply source terminal and a point of reference potential and having an output coupled to the output terminal, and means for detecting first and second ranges of voltages at the power supply source terminal and for producing first and second control voltages, respectively, to control the first and second switches.

Abstract: A process for the fabrication of "low temperature"-gate MESFET structures, i.e., gate metal deposition takes place after annealing of an n.sup.+ -implant that form source- and drain- contact regions. The process permits self-alignment of all three important MESFET parts, namely, the implanted contact regions, and both, the ohmic, as well as the gate, contact metallizations. In the process, a multi-layer "inverted-T" structure is used as a mask for the n.sup.+ -implant and for the ohmic and gate metallizations. The upper part of the "inverted-T" is a so-called dummy gate which is replaced by the Schottky gate after ohmic contact metal deposition. The source-gate and drain-gate separations are determined by the shoulders of the lower layer of the "inverted-T", the shoulders being obtained using sidewall techniques.

Abstract: A method or process is provided for making a semiconductor structure which includes the steps of forming in a semiconductor body a P/N junction and an opening in an insulating layer disposed on the surface of the semiconductor body. A trench is then formed in the semiconductor layer having a sidewall located along a given plane through the opening and through the P/N junction. An insulating material is disposed within the trench and over the insulating layer and a block or segment of material is located over the trench so as to extend a given distance from the trench over the upper surface of the body. The insulating material and the block are then etched so as to remove the block and the insulating material located along the sides of the block. A layer of low viscosity material is formed over the semiconductor body so as to cover the remaining portion of the insulating material, the layer of low viscosity material and the insulating material having similar etch rates.

Abstract: A test circuit or system is provided wherein data is stored in circuits or cells of an array or matrix with the use of conventional or normal operating voltages. Voltages at internal nodes of the circuits or cells are altered to magnitudes beyond the normal operating ranges, which includes significantly decreasing the offset voltage, for a short period of time and then the stored data is read out at normal voltages and currents and compared with the data written into the circuits or cells.

Abstract: A surface is subjected to a light field whose intensity is periodically modulated in a vertical direction to evaluate a scattered light pattern. The light field is obtained from interference between a first or central beam with vertical incidence and two symmetrical laterally disposed beams with oblique incidence. All beams are focussed to a common spot if the profile is obtained by scanning the surface or are superimposed as collimated beams if large area profiling is desired. The surface is imaged onto a diaphragm which selects appropriate locations of the surface for measurements by a photodetector to record sinusoidal intensity variations that are obtained when the light is periodically shifted in a vertical direction by phase modulating the first or central beam with respect to the lateral beams.

Abstract: Design/test technique to facilitate improved long-term stability testing of static memory arrays with high inherent data retention characteristics at extremely small standby current requirements. The test concept is based on the fact that defects in the standby condition system of a memory array have a bearing on the word line standby potential. Detection of word line potentials differing from their nominal value defined for the standby state, i.e., in the unselected operation mode, is accomplished by performing a disturb write operation into the partly or totally unselected array. As a result cells along a defective word line are less disturbed than those along a goood or normal word line. This inverted error pattern is used for screening defect word lines which otherwise would show up as long-term data retention problems.

Abstract: A method for the fabrication of self-aligned MESFET structures with a recessed refractory submicron gate. After channel formation on a semi-insulating (SI) substrate, which may consist of a III-V compound semiconductor such as GaAs, with subsequent annealing, refractory gate material is deposited and patterned. This is followed by the overgrowth of a highly doped contact layer of, e.g., GaAs, using MOCVD of MBE processes resulting in poly-crystalline material over the gate "mask" and mono-crystalline material on exposed semiconductor surfaces. Next, the poly-crystalline material is removed in a selective etch process, this step being followed by the deposition of source and drain electrodes. In order to further improve process reliability, insulating sidewalls are provided at the vertical edges of the gate to avoid source-gate and drain-gate shorts.

Abstract: An off-chip driver circuit is provided which includes a pull-up device disposed between an output terminal and a first voltage dropping diode which is connected to a first voltage supply source and a first voltage limiting circuit connected to the common point between the pull-up device and the voltage dropping diode. The off-chip driver circuit further includes an input inverter circuit having an output connected to the control element of the pull-up device. The inverter circuit has a P-channel field effect transistor and an N-channel field effect transistor serially connected with a second voltage dropping diode which is connected to the first voltage supply source and a second voltage limiting circuit connected to the common point between the second voltage dropping diode and the P-channel field effect transistor of the input inverter.

Abstract: A BICMOS binary logic circuit or system is provided which includes P-channel and N-channel transistors, a bipolar transistor having a base connected to the drain of the P-channel transistor, a diode, preferably a Schottky barrier diode, connected between the emitter of the bipolar transistors and the drain of the N-channel transistor, a capacitor load connected to the emitter of the bipolar transistor and an input terminal connected to control electrodes of the P-channel and N-channel transistors.

Abstract: A substrate bias generator or circuit is provided which includes a charge pump having a series circuit with first and second nodes connected between a semiconductor substrate and a point of reference potential. A first voltage having a first phase is coupled to the first node and a second voltage having a second phase is coupled to the second node. A field effect transistor is connected between the substrate and the second node and the control electrode of the transistor is connected to the first node. The series circuit includes first and second devices, preferably diodes, with the first device being connected between the first node and the point of reference potential and the second device being connected between the first and second nodes.

Abstract: A simple process is provided for making two self-aligned recessed oxide isolation regions of different thicknesses which includes the steps of defining first and second spaced apart regions on the surface of a semiconductor substrate, forming a protective layer over the first region, forming a first insulating layer of a given thickness within the second region while the first region is protected by the protective layer, removing the protective layer from the first region and forming a second insulating layer thinner than that of the first layer within the first region. Field regions may be ion implanted prior to forming the insulating layers.

Abstract: This invention provides a differential circuit having first and second transistors interconnected by a third transistor which is symmetrically constructed. A current source is selectively connected to the base of the third transistor. When the current source is connected to the base of the third transistor, the third transistor is saturated, forming a very low impedance path between the first and second transistors. However, when the current source is disconnected from the base of the third transistor, the third transistor impedes the voltage breakdown path between the bases of the first and second transistors. The differential circuit is particularly useful in an improved compact magnetic media system wherein both the stored signal and the write signal or voltage are applied to the bases of the first and second transistor of the circuit without the high write voltages destroying the high performance first and second transistors.

Abstract: Semiconductor integrated word organized store comprising a two-dimensional array of bistable storage cells linked by orthogonal word lines and pairs of bit lines. Each cell consists of two cross-coupled merged transistor logic (MTL) gates having a structure providing a vertical inverting base transistor and two complementary lateral injector transistors. A cell is driven by read/write logic pulses applied to the word lines and bit lines only. To read the contents of a word from the array, read logic drives the read injectors of the cells constituting the word at a high injector current level and the read injectors of all other cells at a low injector current level. To select a word for writing, the read logic drives the read injectors of the cells comprising the word at a low injector current level and all other cells at a high injector current level. The contents of the selected word may then be changed by differentially driving the cell write injectors over the bit lines.

Abstract: A constant biasing circuit is made to maintain a fixed difference of potential between two circuit nodes A and B otherwise at floating potential levels. The biasing circuit is made of series connected complementary transistors disposed between the circuit nodes A and B and having their gate electrodes respectively connected to opposite voltages of, e.g., +5 volts and -5 volts.

Abstract: A method is provided for making a planar surface on a semiconductor substrate having a trench or groove formed therein and filled with a material such as an organic material which may be used to electrically isolate one region of the substrate from an adjacent region of the substrate.

Abstract: A memory is provided which includes a semiconductor substrate having a diffusion region disposed therein, first, second, third and fourth storage capacitors, first, second, third and fourth switching or transfer devices for coupling the first, second, third and fourth storage capacitors, respectively, to the diffusion region, a common conductor connected to the diffusion region and means for selectively activating the switching devices. In a more specific aspect of this invention, a plurality of groups of the four storage capacitors are arranged so that each of these capacitors is selectively coupled to the common conductor. In another aspect of this invention, the storage capacitors of the plurality of groups are arranged in parallel rows with the common conductor arranged obliquely to the direction of the rows of storage capacitors.

Abstract: A memory array is provided which includes a common sense line to which is connected first and second series of cells, each cell of each series includes a storage capacitor, a switching device and a bit line connected to a plate of the storage capacitor, with a common word line connected to the control electrode of each of the switching devices. The switching devices, preferably field effect transistors, of each series of cells have progressively higher threshold voltages beginning at the sense line, and the voltage applied to the common word line has a magnitude greater than that of the highest threshold voltage. Data is stored into or read from the storage capacitors by selecting the common word line and the bit line of the desired cell in a sequential manner.