Abstract: A system manipulates molecules using a set of proximal probes such as those used in atomic force microscopes. An electrostatic pattern is placed on a set of proximal probes such that each proximal probe may exert an electrostatic force. A molecule is captured using those electrostatic forces, after which the molecule can be manipulated while the molecule remains captured by the proximal probes. The electrostatic pattern can be modified such that the molecule moves and/or rotates over the set of proximal probes while the molecule remains captured by the set of proximal probes. The electrostatic pattern can be used to bend or split the molecule while the molecule remains captured by the set of proximal probes, thereby allowing the system to engage the molecule in chemical reactions, e.g., to act as a synthetic catalyst or a synthetic enzyme.

Abstract: A system and method for accurately modeling an asynchronous interface using expanded logic elements are provided. With the apparatus and method, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.

Abstract: A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR™ DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less logic is needed for the mask calculation because only 144 of the 256 possible byte values are decoded. The mask value is generated and stored in a mask array. Independently, the write data is stored in a write buffer. The mask value is utilized to generate a write mask command. Once the write mask command is issued, the write data and the mask value are transmitted to a multiplexer. The multiplexer masks the write data using the mask value, so that the masked data can be stored in the XDR DRAMS.

Abstract: A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.

Abstract: A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity checking and other techniques, there are tradeoffs. Time required to perform the parity check, for example, can cause system latencies. Therefore, to reduce latencies, a trusted register can be included into a memory system to allow for immediate access to one piece of trusted data. By being able to read one piece of trusted data, the system can overlap the parity checking and delivery of a location of data with the reading of the next location of data from the memory array. Hence, a full cycle of latency can be eliminated without the reduction of the clock frequency.

Abstract: An object editor capable of displaying a set of application software objects, which may include objects with a dynamic reflection capability (“reflective objects”), includes an object oriented configuration model instance (CMI), a generic adapter, and a UI framework. The CMI is particular to the set of application objects to be edited and defines a particular view of these objects to be provided by the editor. The CMI is external to the generic adapter and includes settings that control which application objects will be accessed and the manner of access. The generic adapter reads the de-serialized CMI's current settings, selectively accesses the set of application objects to be edited and their attributes as dictated by the CMI settings, and passes the accessed information to the UI framework for display.

Abstract: In an electronic spreadsheet, an example of a solution provided here comprises defining boolean variables in a table, referencing the boolean variables in one or more cells, and determining the content of the cells. Such a solution may involve managing the boolean variables (also referred to as options) by creating a new option, renaming an existing option, or changing the status of an existing option, for example.

Abstract: An arbitration structure, a method, and a computer program are provided for an arbitration scheme that can handle a plurality of memory commands in an operating system. Typically, in a memory system there are three types of memory commands: periodic, read, and write. An arbitration scheme determines the order of priority in which these commands are executed. This arbitration scheme is flexible because it contains a read/write priority module, which can be programmed to execute any order of priority combination of read and write commands. This enables an arbitration scheme for any memory system to be easily programmed for maximum efficiency.

Abstract: An apparatus and method for providing a multi-core integrated circuit chip that reduces the cost of the package and board while optimizing performance of the cores for use with a single voltage plane. The apparatus and method of the illustrative embodiments make use of a dynamic burn-in technique that optimizes all of the cores on the chip to run at peak performance at a single voltage. Each core is burned-in with a customized burn-in voltage that provides uniform power and performance across the whole chip. This results in a higher burn-in yield and lower overall power in the integrated circuit chip. The optimization of the cores to run at peak performance at a single voltage is achieved through use of the negative bias temperature instability affects on the cores imparted by the burn-in voltages applied.

Abstract: An electronic business operations measurement system and method are provided. The system and method provide a measurement process in which a script is provided for execution by a first probe and a second probe in order to measure the performance of an application. The measurements of the first and second probes may then be mapped to threshold values. The first probe may execute the script on a first data processing device on which the application executes. The second probe may execute the script on a second data processing device remotely located from the first data processing device on which the application executes. The measurements of the performance performed by the second probe may be adjusted, through conversion of the measurement data using a conversion algorithm, to represent a type of network connection for communicating with the application that is common to end users of the application.

Abstract: A method and apparatus for encryption of data are provided, in which the data is made up of a series of data items (600). The data items (600) maybe bytes of data or blocks of data. The method includes providing a plurality of encryption algorithms (604), selecting when to change encryption algorithm (601), selecting which encryption algorithm to change to (603), wherein each selection is carried out by applying a Chaotic and/or Catastrophic equation. The plurality of encryption algorithms (604) have index numbers and the generation of an index number by applying the Chaotic or Catastrophic equation selects an encryption algorithm. The selection of when to change encryption algorithm may be determined by a Catastrophic event in the Catastrophic equation and the selection of encryption algorithm may be determined by the surface of a Catastrophic curve on which a point lies, wherein each surface corresponds to an encryption algorithm.

Abstract: The present invention provides for a system comprising a first stable voltage module configured to receive a first power supply from a first power supply domain and to generate a first stable voltage in response to the received first power supply. A second stable voltage module is configured to receive a second power supply from a second power supply domain and to generate a second stable voltage in response to the received second power supply. A first set of resistors is coupled to the first stable voltage module and configured in parallel. A second set of resistors is coupled to the second stable voltage module and configured in parallel. A set of capacitors is coupled in parallel to the first set of resistors and the second set of resistors and a plurality of level shifters are coupled to the second set of resistors.

Abstract: A mechanism for measuring duty cycle of a signal under test in an integrated circuit device, such as a microprocessor or system-on-a-chip is provided. The mechanism generates a frequency which is proportional to the duty cycle and which can be measured using common lab or manufacturing equipment. The mechanism may be implemented using simple circuits in a standard complementary metal oxide semiconductor process which requires very little area and can be powered off when it is not being used. The mechanism may include, for example, a low pass filter, a voltage divider for providing calibration reference voltage signals, a voltage to frequency converter, a frequency divider for dividing a frequency signal output so that the frequency of the signal is within a predetermined range, and an output driver and output pad. From the frequency output signal, a duty cycle of the signal under test may be calculated using off-chip equipment.

Abstract: A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set coloring and expected result checking. Based on the characteristics of the system being tested an iterative parallel algorithm is selected from a plurality of possible parallel algorithms. The selected parallel algorithm is then separated into separate program statements for execution by a plurality of processors. A serial version of the selected algorithm is executed to generate a set of expected results. The devised parallel version of the selected algorithm is then run to generate a set of test result data which is compared to the set of expected results. If the two sets of data match, it is determined that the system is operating correctly.

Abstract: A method (300) of distributing software features (particularly software products having a global portion and a user portion necessary for activating the software products) to client workstations of a network; each client workstation has a multi-user operating system, and may be accessed (327-328) with different user profiles each one associated with a corresponding operating context. A distribution package is received (312) in the client workstation; the distribution package includes instructions associated with global activities for the client workstation as a whole or with user activities specific for the single profiles. A distribution agent (running outside the context of a current profile) executes (309-329) only the global activity (even if the workstation is in a logoff condition) and schedules the user activities to be performed when a user next logs onto the workstation.

Abstract: An apparatus and method for verifying glitch-free operation of a multiplexer are provided. The apparatus includes a circuit having a plurality of flip-flop elements that receive as inputs the plurality of clock signals that are inputs to the multiplexer, and a corresponding synchronized output signal of a decoder generated based on control inputs to the decoder. The synchronized output signals from the decoder are used as trigger signals to the plurality of flip-flops. The flip-flops sample the clock signals based upon the trigger signals and provide outputs to a logic gate. The logic gate operates on the outputs from the flip-flops to generate an output signal indicative of whether glitch-free operation is verified or is not verified.

Abstract: A level shifter apparatus and method for minimizing duty cycle distortion are provided. The level shifter includes a bank of comparators each having an associated threshold built into it. The comparators compare a difference in source voltages for two power domains to these built-in thresholds and output a signal indicative of whether the threshold is exceeded. The output signals from the comparators are provided to a thermometric decoder which generates control signals based on these output signals. The control signals are used to control stages in a level shifter for modifying the voltage output of the level shifter. Individual stages may be enabled to thereby monotonically modify the voltage output of the level shifter and thereby decrease a time required to achieve a voltage having a level that causes a state change in a driven circuit. As a result, duty cycle distortion is minimized and maximum operational frequency is increased.

Abstract: The present invention provides for correcting excessive pulse widths using incremental delays. The pulse width is evaluated through a correction block and leak detector. An acceptable pulse passes through an interconnect directly to the clock output. Unacceptable pulses are sent through a block delay module that incorporates a series of delay sub-blocks that disconnect and reset in accordance with a pre-programmed total delay time. The conditioned clock pulse is resent through a node to the correction block and leak detector where it is reevaluated. If the pulse is acceptable, it is sent to the clock output. If the pulse is found unacceptable, it is recycled again. A high low clock pulse shuttle determines and alters the high or low state of the clock pulse to ensure a correct output to downstream dependent devices.

Abstract: The present invention provides for a method for computer program code optimization for a software managed cache in either a uni-processor or a multi-processor system. A single source file comprising a plurality of array references is received. The plurality of array references is analyzed to identify predictable accesses. The plurality of array references is analyzed to identify secondary predictable accesses. One or more of the plurality of array references is aggregated based on identified predictable accesses and identified secondary predictable accesses to generate aggregated references. The single source file is restructured based on the aggregated references to generate restructured code. Prefetch code is inserted in the restructured code based on the aggregated references. Software cache update code is inserted in the restructured code based on the aggregated references. Explicit cache lookup code is inserted for the remaining unpredictable accesses.

Abstract: An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.