Abstract: A low inductance via arrangement for multilayer ceramic (MLC) substrates is provided. With the MLC substrate and via arrangement of the illustrative embodiments, the via-field inductance for a given contact pad array is reduced. This reduction is achieved by the introduction of T-jogs and additional vias. These T-jogs and additional vias form additional current paths that cause additional parallel inductances that reduce the via-field inductance. In one illustrative embodiment, the additional T-jogs and vias are added to a center portion of a contact pad array. The T-jogs are comprised of two jogs in a wiring layer of the MLC, each jog being toward a via associated with an adjacent contact pad in the contact pad array. These additional T-jogs and vias form additional current loops parallel to the existing ones which thus, reduce the total inductance of the via-field.

Abstract: Authentication mechanisms for accessing one or more applications by a user by using collaborative agents for automating authentication to the one or more applications. The use of collaborative agents obviates a need for the user to remember fortified authentication credentials for each application.

Abstract: Mechanisms for splitting responsibilities for communicating with an endpoint between a device driver and device driver services are provided. With these mechanisms, the device driver is responsible for managing queues for communicating requests between applications in a logical partition and the endpoint. The device driver further invokes memory management via device driver services. The device driver services are responsible for managing memory accessible by the endpoint, including the address translation and protection table (ATPT) or a root complex and the address translation caches (ATCs) of the endpoint. The device driver services may associate untranslated addresses for data structures used to communicate between a system image and the endpoint. The endpoint may request translations of the untranslated addresses and may cache the translations in the ATCs.

Abstract: Mechanisms are provided for estimating requirements for completion of a project. These mechanisms, which may be implemented by a data processing system, define general project factors for a general kind of project as well as analysis rules for this general kind of project. A complexity matrix that defines a plurality of complexity measures for a plurality of project factors for a specific project is provided. The analysis rules are applied to the project factors of the complexity matrix to generate a single complexity measure for the specific project. This complexity measure is used by an estimation mechanism to generate an estimate of requirements for completing the project. Exceptional combinations of project factors may be defined to force the single complexity measure to a maximum value when the conditions of the exceptional combinations are met by the complexity measures of the complexity matrix for a specific project.

Abstract: A system and method for application fault tolerance and recover using topologically remotely located computing devices are provided. A primary computing device runs one instance of an application (i.e. the primary application instance) at a production site and an active standby computing device runs a second instance of the application (i.e. the shadow application instance) at a recovery site which may be topologically remotely located from the production site. The two instances of the application are brought into a consistent state by running an initial application “checkpoint” on the primary computing device followed by an application “restart” on the active standby computing device. Events occurring in the primary application instance may be automatically and continuously recorded in a log and transferred to the recovery site using a peer-to-peer remote copy operation so as to maintain the states of the application instances consistent.

Abstract: A programmable local clock buffer for integrated circuit devices which is capable of varying initial settings is provided. The illustrative embodiments allow a single type of local clock buffer (LCB) to be used throughout an integrated circuit design while still being able to provide differing initial offsets and pulse widths for different local circuitry portions of the integrated circuit design. Delay circuit paths are provided, which provide discreet delay values, within the LCB that can be chained together when the LCB is instantiated to set the initial offset and pulse width values. When an LCB is instantiated in the integrated circuit device design, various ones of the delay circuit paths are connected together with the existing circuit paths of the LCB, i.e. the circuit paths that provide the pre-established offset and pulse width values, in order to set the initial offset and pulse width values for the LCB.

Abstract: Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e.g., an on-chip voltage, which approximates a nominal circuit voltage, such as produced by the application of other portions of the sequence of states in the same or different test sequences. For example, hold state cycles or shift-scan state cycles may be inserted or removed prior to test state cycles in the test pattern waveform. The insertion/removal shifts the occurrence of the test state cycles within the test pattern waveform so as to adjust the voltage response of the test state cycles so that they more closely approximate a nominal voltage response. In this way, false failures due to noise in the voltage supply may be eliminated.

Abstract: The invention entails identifying the parties involved in a process of handling personally identifiable information; identifying the data involved in said process; classifying the data; expressing each relationship between each pair of said parties in terms of a privacy agreement; and representing the parties, data, and privacy agreements graphically in one or more privacy agreement relationship diagrams. The invention has the advantage of identifying opportunities to reduce privacy-related risks, including identifying unnecessary exchanges of data, for possible elimination, and identifying opportunities to transform data into a less sensitive form. Privacy agreements are based on a limited set of privacy-related actions: access, disclose, release, notify, utilize, update, withdrawConsent, giveConsent, delete, anonymize, depersonalize, and repersonalize. One aspect of the present invention is a method for improving the handling of personally identifiable information.

Abstract: Mechanisms for generating constraint preserving testcases in the presence of dead-end constraints are provided. A balance between precision and computational expense in generating the testcases is achieved by establishing a sliding window of constraint solving for a selected number of K time-steps in the future from a current time-step. The testcases solve for the constraints for the next K time-steps at every state of a netlist instead of just trying to solve the constraint for the present time-step. K is determined by determining, for each input, either a minimum length path depth or maximum length depth path from the input to the constraint. The largest depth value for the inputs to the netlist is then utilized as the depth for the netlist. This depth then is used to define the width of the sliding window of constraint solving.

Abstract: The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The data for such future load instructions can be prefetched from a distant cache or main memory such that when the load instruction is re-executed (non speculative executed) after the stall condition expires, its data will reside either in the L1 cache, or will be enroute to the processor, resulting in a reduced execution latency. When an extended stall condition is detected, load lookahead prefetch is started allowing speculative execution of instructions that would normally have been stalled.

Abstract: A system and method of error recovery for backup applications that utilizes error recovery logic provided in the storage controller itself are provided. With the system and method, error recovery logic is provided in the storage controller for generating and maintaining error recovery logs for one or more backup operations of one or more backup applications running on one or more host systems. The backup applications may utilize an established set of commands/API function calls to invoke the error recovery logic on the storage controller. At the initiation of the backup operation, the storage controller assigns a unique identifier to the backup operation and returns this identifier to the backup application. The backup application may then use this identifier to initiate error recovery operations or commit changes made during the backup operation via the storage controller. Thus, the storage controller offloads the burden of error recovery from the backup applications.

Abstract: Mechanisms for communicating with an I/O device or endpoint using a queue data structure and pre-translated addresses associated with the queue data structure are provided. With the mechanisms, a device driver invokes device driver services for initializing address translation and protection table (ATPT) entries in a root complex for the queue data structure. The device driver services return untranslated addresses to the device driver which are in turn provided to the I/O device or endpoint. The I/O device or endpoint may then request a translation of these untranslated addresses and store them in the I/O device or endpoint prior to receiving an I/O operation targeting the queue data structure. The cached translation may be used to directly access the queue data structure from the I/O device or endpoint by bypassing the root complex's address translation facilities.

Abstract: Mechanisms for communicating with a memory registration enabled adapter, such as an InfiniBand™ host channel adapter, are provided. With the mechanisms, device driver services may be invoked by a device driver for initializing address translation entries in an address translation data structure of a root complex. An address of a device driver data buffer data structure and registration modifiers may be passed by the device driver to the device driver services. The device driver services may create address translation data structure entries in the address translation data structure associated with the root complex and memory registration (MR) address translation entries in a MR address translation data structure of the adapter. The MR address translation data structure may then be used with I/O operations to bypass the address translation data structure associated with the root complex.

Abstract: A method for controlling access to a process to be executed on a data processing system is provided. An interface is provided for coupling a security device to the data processing system. The security device is a separate hardware device from the data processing system. User input of an identifier for accessing the security device is received, the identifier is verified, and the security device is accessed, in response to the identifier being verified, to obtain authentication data for the process to be executed on the data processing system. The authentication data is injected into a login process associated with the process to be executed to automatically authenticate a user to the process to be executed. The security device uses private-public key authentication to authenticate the user to the process to be executed without the user being aware that private-public key authentication is being performed.

Abstract: Mechanisms are provided for performing capacity upgrade on-demand operations for input/output(I/O) adapters of a data processing device. The mechanisms involve providing a data processing device with additional I/O adapters in excess of current I/O capacity requirements of an owner/user of the data processing device. These additional I/O adapters remain in an inactive state after booting of the data processing device until they are specifically activated by the owner/user. Although inactive, memory resources are reserved for the address translation data structures for these inactive I/O adapters. The owner/user may, at a later time, obtain an activation code from a provider of the data processing device and enter the activation code into a hardware management console to thereby activate the additional I/O adapters. The reserved memory resources are then utilized to initialize the address translation data structures for these now active I/O adapters.

Abstract: An apparatus and method for using electrical fuses (eFuses) to store phase-locked loop (PLL) configuration data are provided. With the apparatus and method, a portion of the eFuses present in the integrated circuit are reserved for the PLL configuration data. Upon power up, a power up controller and eFuse controller direct the sensing and serial transfer of the data in the portion of eFuses to the PLL under the reference clock. When the transfer is complete, the power up controller directs the PLL logic to load the configuration data and start. The mechanism of the present invention allows manufacturing to tailor the PLL configuration on a given device based on the characteristics of that device and its intended usage. Thus, the same PLL may be used in the same or different architectures to perform different operations based on the configuration data passed into the PLL from the eFuses.

Abstract: An example of a solution provided here comprises receiving a text definition signal, defining a first portion of text for folding, receiving a signal for hiding, and in response to the signal for hiding, displaying to at least one user a text view without the first portion, and a clue as to what is hidden.

Abstract: Mechanisms for generating a set of one or more elements of a fingerprint for a document, the document comprising a semantic construct having one or more ordered words, are provided. With these mechanisms, a range of sizes for a fingerprint element is defined and ordered words of the semantic construct are divided into a set of one or more mutually exclusive fingerprint elements. Each of the one or more mutually exclusive fingerprint elements includes a number of adjacent words, the number being within the range of sizes for a fingerprint element. Responsive to a determination that the set of mutually exclusive fingerprint elements excludes a word from the semantic construct, the excluded word is discarded.

Abstract: An example of a solution provided here comprises: performing a benefits simulation, performing a process simulation, performing an information technology simulation, performing a value simulation, providing interactions among the simulations, and representing with the simulations the use of at least one business transformation outsourcing service by a client organization.

Abstract: A buffer, a method, and a computer program product for DMA transfers are provided that are designed to save memory space within a local memory of a processor. The buffer is a return buffer with a portion reserved for DMA lists. A DMA controller accomplishes DMA transfers by: reading address elements from a DMA list located in the DMA list portion; reading the corresponding data from system memory; and copying the corresponding data to the return buffer portion. This buffer saves space because when the buffer begins to fill up the corresponding return data can overwrite the data in the DMA list. Accordingly, the DMA list overlays on top of the return buffer, such that the return data can destruct the DMA list and the extra storage space for the DMA list is saved.