Abstract: A method (300) and a corresponding system for managing associations in the CIM model are proposed. An association is modeled by a particular class, which includes two or more references to other classes; the association is implemented by a corresponding provider. Whenever a management application (such as a performance monitor) needs to access the association, a corresponding request is transmitted (309) to the provider. In response thereto, the provider enumerates (315) all the resource objects instantiating the references of the association, and creates (324) an instance of the association for any combination. In the method of the invention, the provider further sets (318,327) a property of each instance of the association, according to dynamic characteristics of the corresponding resource objects. In this way, an active association is provided, allowing cross-analysis of the resource objects participating in the association.

Abstract: An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.

Abstract: Methods and apparatus are provided for assisting a user who is editing a markup document on a computer. The user is presented with the markup document on a display of the computer for editing and provided with grammatical assistance based on a grammar inferred from current content of the markup document. The grammar may be inferred and updated automatically after the markup document is loaded or edited. The assistance provided may be based on a combination of an inferred grammar and a real grammar. The markup document can be an extensible markup language (XML) document.

Abstract: Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.

Abstract: A method is provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expected test results data. The test stimuli are sent to the SoC under test via a peripheral communication interface between the previously verified SoC and the SoC under test. The SoC under test generates actual test result data that is output to the previously verified SoC. The previously verified SoC may then compare the expected test results data with the actual test result data generated by the SoC under test to determine if they match. If the two sets of data do not match, then a mismatch notification may be generated and output.

Abstract: A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

Abstract: An eFuse data alignment verification apparatus and method are provided. Alignment latches are provided in a series of latch units of a write scan chain and a logic unit is coupled to the alignment latches. A sequence of data that is scanned-into the series of latch units of the write scan chain preferably includes alignment data values. These alignment data values are placed in positions within the sequence of data that, if the sequence of data is properly scanned-into the series of latch units, cause the data values to be stored in the alignment latches. The logic unit receives data signals from the alignment latches and determines if the proper pattern of data values is stored in the alignment latches. If the proper pattern of data values is present in the alignment latches, then the data is aligned and a program enable signal is sent to the bank of eFuses.

Abstract: A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.

Abstract: An encryption apparatus and method for providing an encrypted file system are provided. The encryption apparatus and method of the illustrative embodiments uses a combination of encryption methodologies so as to reduce the amount of decryption and re-encryption that is necessary to a file in the Encrypted File System in the event that the file needs to be modified. The encryption methodologies are interleaved, or alternated, with regard to each block of plaintext. In one illustrative embodiment, Plaintext Block Chaining (PBC) and Cipher Block Chaining (CBC) encryption methodologies are alternated for encrypting a sequence of blocks of data. The encryption of a block of plaintext is dependent upon the plaintext or a cipher generated for the plaintext of a previous block of data in the sequence of blocks of data so that the encryption is more secure than known Electronic Code Book encryption methodologies.

Abstract: The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The execution of such future instructions can initiate a prefetch of data or instructions from a distant cache or main memory, or otherwise make forward progress through the instruction stream. In this manner, when the instructions are re-executed (non speculatively executed) after the stall condition expires, they will execute with a reduced execution latency; e.g. by accessing data prefetched into the L1 cache, or enroute to the processor, or by executing the target instructions following a speculatively resolved mispredicted branch.

Abstract: A Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.

Abstract: An example of a solution provided here comprises receiving as input at least one event (chosen from an event generated by an application probe, and an event generated by a component probe), and providing graphical output based on said inputs, whereby a user correlates a component problem with a performance problem affecting an application. Methods connected with graphics for end to end component mapping and problem—solving in a network environment, systems for executing such methods, and instructions on a computer-usable medium, for executing such methods, are provided.

Abstract: A system and method are provided to allow a user to update a computer system without having to interact with an initialization, or configurator software utility, or program. More particularly, the present invention allows a system provider, manufacturer, or service provider to create an installation file that, when provided to a user, will configure a system to accommodate newly added/removed hardware automatically. A base model and a new model of the system are maintained. The new model will include one or more different configurations, such as new graphics adapters, communications adapters, I/O controllers, or the like. The provider will have created a recovery/install image to be used with the base model. An operating system including a configurator program will be running on both the base model system and new model system. Software, such as device drivers, to be used with the new model's changed hardware configuration is installed on the new model system and initialized using its configurator program.

Abstract: The present invention provides for authenticating a message. A security function is performed upon the message. The message is sent to a target. The output of the security function is sent to the target. At least one publicly known constant is sent to the target. The received message is authenticated as a function of at least a shared key, the received publicly known constants, the security function, the received message, and the output of the security function. If the output of the security function received by the target is the same as the output generated as a function of at least the received message, the received publicly known constants, the security function, and the shared key, neither the message nor the constants have been altered.

Abstract: A method (300) and system for preventing private information to be collected and sent to the INTERNET without the consent of a user of a client computer. Every time the user wishes (317) to run a new application program, an isolator engine is invoked (303). The isolator engine intercepts (329) all the output operations (327) of the application program attempting to send messages to the INTERNET. Each message is compared (330-345) with a privacy list storing a series of strings (such the name of the user, his or her private e-mail address); if a match occurs, the user is asked (352) whether he or she desires to continue or abort execution of the application program.

Abstract: In remote control systems (as in many other circumstances) the color representation of a bitmap is one of the heaviest factor in term of storage occupation and speed of transmission. Often, only a limited number of colors is actually used by a bitmap, so that the bit pattern of the single pixels is bigger than what is really needed to represent all the possible different colors. With the present invention, in case the number of colors does not exceed a predetermined thresholds, a palette table containing all the colors used in the bitmap is created. The pixel representations in the bitmap are then replaced by a pointer to the corresponding entry in the palette table. This allows to reduce the total size of the bitmap. The reduced bitmap is then transmitted together with the associated palette table. The receiving computer (the controller in a remote control system) is able to rebuild the original bitmap with the help of the palette table.

Abstract: A concealed panel locking mechanism is provided which may be used to secure the contents of a container in a manner that is not discernable to an uninformed individual viewing the container. In one exemplary embodiment, the locking mechanism includes one or more channels formed into a central area of a panel of material. A locking member within the one or more channels is movable along the channel to either engage or disengage the locking member from a recess formed in a side wall of the container. In one embodiment, the locking member is not physically accessible from outside the channel by a human being but is formed from a ferromagnetic material that is moved within the channel by a magnetic force generated by a suitable strength magnetic key placed on the outside surface of the panel.

Abstract: The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to the output of the first divider, thereby lessening current surges.

Abstract: A system and method for reducing noise in a multi-layer ceramic package are provided. With the system and method, additional shielding wires are inserted into the reference planes wherever there are no signal vias present. These additional lines in the reference planes force stronger signal interaction with the reference (vdd/gnd) thereby reducing the interaction between the signals in the signal layers. As a result, the noise present in the signals of the signal layers is reduced.

Abstract: A method (300) of editing program code is proposed. The program code consists of main instructions written in a high-level language. Typically, the program code further includes one or more sets of service instructions, which are not directly connected to a desired algorithm (such as tracing instructions for debugging purposes, performance measuring instructions, and the like). In the solution of the invention, each set of service instructions is enclosed (321-322) between a pair of predefined comments defining a starting tag and an ending tag. An editor of the program code is provided with commands for automatically disabling (341) the service instructions (converting them into corresponding comments); at the same time, the disabled instructions are condensed (340) on the monitor. Additional commands are available for automatically enabling (368) and restoring (367) the service instructions.