Abstract: An improved output buffer having a digital output slew control and compensation for manufacturing process variations. Output slewing is accomplished by sequencing digital drive signals to paralleled output transistors. In one embodiment, a pre-driver sequences the drive signals by using the propagation delays of serially coupled digital logic gates to reduce power supply droop and/or ground bounce. The output transistors are turned off substantially simultaneously to avoid undesirable power supply DC current flow when the output buffer changes state. Programmably configuring the number of paralleled transistors that may be turned on at any given time allows a user to compensate for manufacturing process variations and determine the output impedance/drive capacity of the buffer.

Abstract: This disclosure relates to a cell-placeable variable-frequency digitally controlled oscillator (DCO) that consumes approximately the same current in a fast process corner as in the case of a slow process corner. By modulating the effective channel length of transistors in inverters, a fast process DCO may be slowed down to a desired frequency at nearly the same current consumption as that of a slow process DCO.

Abstract: The invention includes a method and apparatus for synchronizing a first processor with a second processor. The method includes storing in a register parallel bits of data from the first processor, wherein at least one bit of data is a logic ONE. An output signal is formed from the one bit of data in the register. The output signal is sent as an interrupt signal to an interrupt terminal of the second processor for synchronizing the first processor with the second processor. The method may be used with a memory mapped register or an off-core register. The first and second processors may each be a digital signal processor (DSP) or any other type of processor.

Abstract: A system for a backplane that employs i) an adjustment of positive-to-negative (P-N) driver skew of a transmit signal of a relatively high-speed differential driver to reduce far-end crosstalk, ii) a high-speed differential subtraction circuit combining a gain-adjusted replica of at least one transmit signal with a received signal to reduce near-end crosstalk, and iii) a phase-locked loop (PLL) synchronization circuit to align timing events between a set of near-end and far-end high-speed interfaces.

Abstract: Certain embodiments of the present invention relate to techniques for tuning or measuring operational features of amplifiers, such as the transconductance of operational transconductance amplifiers (OTAs) and the gain of variable gain amplifiers (VGAs). Each technique employs (at least) two phases that involve the application of different input voltages. The results of the multiple phases are then combined to generate a final result that negates or reduces the effects of real-world properties such as finite output impedances and offset voltages.

Abstract: A system employs space-time coding characterized at the transmitter by bit-interleaved coded modulation (BICM) combined with multi-carrier Orthogonal Frequency Division Multiplexing (OFDM) modulation. Space-Time coding techniques improve transmission efficiency in radio channels by using multiple transmit and/or receive antennas and coordination of the signaling over these antennas. Bit-interleaved coded modulation provides good diversity gain with higher-order modulation schemes that employ binary convolutional codes. OFDM modulation allows for wideband transmission over frequency selective radio channels. A receiver demodulates the OFDM signal and applies multi-input, multi-output (MIMO) demapping to estimate the BICM encoded bitstream. After deinterleaving of the BICM encoded bitstream, maximum a posteriori (MAP) decoding is applied to the resulting bit stream to generate soft output values.

Abstract: A method and system are for reducing power consumption in a multi-way set-associative cache memory. During a first clock cycle, in response to an address, an associated set is identified in the cache memory. The address is compared to respective tag portions of blocks in the associated set, and a signal is output in response thereto. During a second clock cycle, in response to the signal indicating a match between one of the blocks and the address, a non-tag portion of the matching block in the associated set is read, while a non-matching block in the associated set is disabled.

Abstract: A wireless receiver detects signals received at two or more antennas, with each antenna coupled to an input receive chain. A switch is employed to couple selected input receive chains to one or more corresponding output receive chains during listening, coarse-detection, and fine-adjustment modes. At least one channel selection filter (CSF) is employed in each output receive chain, and the receiver employs sub-ranging. During idle mode, one antenna's input receive chain is connected to two or more CSFs to detect the packet. When the packet is detected, during a coarse-adjustment mode, the CSFs are reconfigured to couple each antenna's input receive chain to a corresponding output receive chain using low-gain signals. During fine-adjustment mode, the various gains are adjusted to be either high- or low-gain to maintain signals within the dynamic range of the corresponding CSFs.

Abstract: In a data recovery circuit, multiple slicer outputs of incoming data for each data bit, e.g., one or more slicer outputs taken at or near the center of the eye and one or more slicer outputs taken at or near the leading edge and/or trailing edge of the eye, are processed in a manner that reduces the bit-error rate relative to the prior art. The data recovery circuit may be combined with state-of-the-art clock recovery circuits to yield improved clock and data recovery (CDR) circuits.

Abstract: A maximum a posteriori (MAP) processor employs a block processing technique for the MAP algorithm to provide a parallel architecture that allows for multiple word memory read/write processing and voltage scaling of a given circuit implementation. The block processing technique forms a merged trellis with states having modified branch inputs to provide the parallel structure. When block processing occurs, the trellis may be modified to show transitions from the oldest state at time k?N to the present state at time k. For the merged trellis, the number of states remains the same, but each state receives 2N input transitions instead of the two input transitions. Branch metrics associated with the transitions in the merged trellis are cumulative, and are employed for the update process of forward and backward probabilities by the MAP algorithm.

Abstract: Operation of an adaptive filter includes determining a first filter coefficient and determining a second filter coefficient based on the first filter coefficient, in one embodiment, and in another embodiment includes comparing pseudo-error counts generated for each of several time intervals and setting filter coefficients based on the comparison. Adaptive filter coefficient generating apparatus includes a pseudo-error count generator adapted to receive the output of the adaptive filter and to generate counts of pseudo-errors occurring during successive time intervals, and a filter coefficient generator generating filter coefficients for the adaptive filter in response to the pseudo-error counts.

Abstract: A single-axis receiver processes, for example, a complex vestigial sideband (VSB) modulated signal with an equalizer accounting for DC offset within the modulated signal. The DC offset embedded in a received signal may degrade the process of equalization. The equalizer includes a method of blind estimation of the DC offset for removing the DC offset. The estimate is generated by jointly minimizing a Constant Modulus (CM) cost function over equalizer parameters and a DC offset estimate. An arbitrary DC offset the CM cost function admits local spurious minima in terms of the equalizer function. If the DC offset at the receiver is equal to the DC offset inserted at the transmitter, which is equivalent to neglecting the ISI caused by the channel, then only half of the CM equalizer minima remain unchanged.

Abstract: A disc drive system, such as a magnetic or optical recording and/or playback system, for low-data rate applications implements one or more circuit operations, such as read signal detection and related servo functions, as software-based digital signal processing steps in a dedicated software-based processor. The drive system incorporates increased buffering, modified input sample processing techniques, multiplexing of processing functions, and modified automatic gain control techniques to allow circuit operations to be performed with software-based digital signal processing techniques.

Abstract: A receiver for iterative decoding of a received, encoded signal employs slot-based scaling of soft samples. Iterative decoding employs a constituent maximum a priori (MAP) decoder for each constituent encoding of information of the encoded signal. Root mean square (RMS) values for soft samples over a slot are selected for dynamic range scaling. Squared RMS values are combined and equal the squared RMS value for a frame multiplied by a control constant, and this relationship may be employed to derive scaling constants for each slot. Alternatively, the square root of the RMS value multiplied by a constant serves as an SNR estimator that may be employed to scale samples to reduce dynamic range and modify logarithmic correction values for max* term calculation during log-MAP decoding.

Abstract: This invention discloses an inductor including a conducting wire having a winding configuration provided for enclosure in a substantially rectangular box with a mid-plane extended along an elongated direction of the rectangular box wherein the conducting wire intersecting at least twice near said mid-plane.

Abstract: A frequency upconverter using mixers operating on one or more signals and inverted versions thereof and a subtractor, such as a balun, for subtractively combining the mixer outputs to produce an upconverted signal.

Abstract: A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous carbon sacrificial layer as the top layer of the patterned gate electrode structure. Dielectric spacers are formed alongside the gate electrode structure, including alongside the sacrificial amorphous carbon layer. The dielectric spacers extend substantially to the top of the amorphous carbon layer. The amorphous carbon layer is then removed such that the remaining gate structure includes dielectric spacers that have a protruding section that protrudes above the top surface of the remaining gate structure. A nitride layer may be formed over the gate structure. Such a structure prevents exposure of the gate electrode during the formation of self-aligned contacts, and shorting, once the contact openings are filled.

Abstract: In one embodiment, a rake receiver for a spread-spectrum (SS) signal has a plurality of rake fingers corresponding to different multipath components of the SS signal and sampling circuitry generating a stream of samples corresponding to the SS signal. A first rake finger has a detection path detecting symbols based on the samples, a synchronization (synch) path, and a weighting controller. Front-end circuitry in the synch path applies three or more time delays, weighting, and SS correlation to the stream of samples to generate front-end output signals. Back-end circuitry in the synch path generates one or more control signals for controlling the timing of the sampling circuitry based on the front-end output signals. The weighting controller adaptively controls the weighting applied by the front-end synch circuitry to minimize effects of one or more other multipath components associated with one or more other rake fingers of the rake receiver.

Abstract: The present invention provides an apparatus, method and tangible medium storing instructions for determining tonality of an input audio signal, for selection of corresponding masked thresholds for use in perceptual audio coding. In the various embodiments, the input audio signal is sampled and transformed using a compressed spectral operation to form a compressed spectral representation, such as a cepstral representation. A peak magnitude and an average magnitude of the compressed spectral representation are determined. Depending upon the ratio of peak-to-average magnitudes, a masked threshold is selected having a corresponding degree of tonality, and is used to determine a plurality of quantization levels and a plurality of bit allocations to perceptually encode the input audio signal with a distortion spectrum beneath a level of just noticeable distortion (JND).

Abstract: A method is provided for adjusting the resonant frequency of a mechanical resonator whose frequency is dependent on the overall resonator thickness. Alternating selective etching is used to remove distinct adjustment layers from a top electrode. One of the electrodes is structured with a plurality of stacked adjustment layers, each of which has distinct etching properties from any adjacent adjustment layers. Also as part of the same invention is a resonator structure in which at least one electrode has a plurality of stacked layers of a material having different etching properties from any adjacent adjustment layers, and each layer has a thickness corresponding to a calculated frequency increment in the resonant frequency of the resonator.