Abstract: In an amplifier system that linearizes an amplifier by pre-distorting the input signal prior to amplification, a baseband pre-distortion processor processes the input signal in a digital baseband domain to generate one or more pre-distortion parameters based on the power of the digital baseband input signal. The digital baseband signal is up-converted and D/A-converted into a non-baseband (e.g., IF or RF) signal which is then pre-distorted, e.g., using a phase/gain adjuster or a vector modulator. By generating the pre-distortion parameters at baseband, while pre-distorting the input signal at non-baseband, the amplifier system avoids the cost and inaccuracies associated with analog signal delay and RF power detection of prior-art “all-RF” pre-distortion implementations, while avoiding the wider-bandwidth filtering of prior-art “all-baseband” pre-distortion implementations.

Abstract: Roughly described, a striping algorithm selects a route on which to transmit each next data segment, pseudorandomly from among a subset of eligible routes, the subset being chosen in dependence upon relative channel loading so far. Preferably each ingress node to a switching system chooses an outgoing route for each given next data segment, according to a pseudorandom algorithm, from among a respective given subset containing only those routes via which the amount of data sent from the ingress node during a respective prior time period is no greater than an average of the amount of data sent from the ingress node via any of its outgoing routes during the same prior time period.

Abstract: In one embodiment of the invention, a pulse-generation circuit for generating control signals has clock-delay circuitry for generating a plurality of differently delayed clock signals. Each control signal is generated by a set-reset latch that receives its set and reset signals from different pulse generators operating based on different delayed clock signals from the clock-delay circuitry. In one implementation, the clock-delay circuitry has a partitioned delay block in which different sub-blocks provide different delay functionality to provide the clock-delay circuitry with programmable flexibility.

Abstract: A non-linearity generator operates on a signal between a frequency converter and an amplifier and acts as a postdistorter for the component it follows and as a predistorter for the component it precedes, thus linearizing the overall input-output characteristic of the circuit. Cross-modulation components distorting an injected pilot signal provide a feed-back signal that is used to control the distortion applied by a non-linearity generator. The non-linearity generator can be adapted to cope with widely spaced input tones. The circuit may form part of a transmitter or a receiver.

Abstract: A digital predistorter comprises a module J for producing a counteracting signal Vm1 for combination with the input signal of a power amplifier to correct the output of the amplifier for distorting memory effects within the amplifier. The module J produces the contracting signal Vm1 by convolving (see FIG. 6) functions of the input signal with impulse response characteristics related to the memory effects being corrected. The counteracting signal Vm1 is produced by a function fm and parameters in that function are adjusted to minimize any residual distortion in the amplifier output.

Abstract: In a receiver of a transmission system in which the data transmission rate is not an integer multiple of the spacing between transmission channels, a single oscillator is used to generate both the system clock used to process the data signal as well as the mixing signal used to downconvert the received RF signal to an intermediate frequency (IF). The frequency error in the IF signal that results from mixing the RF signal at a less-than-ideal mixing frequency is compensated by selecting an appropriate mixing signal frequency applied when downconverting the IF signal to baseband. In a transmitter, the mixing signal frequency used to upconvert the outgoing baseband signal to IF is selected to pre-compensate for the frequency error resulting from upconverting the IF signal to RF using a less-than-ideal mixing frequency. In either case, the receiver/transmitter can be implemented without having to provide a dedicated reference oscillator for converting signals between RF and IF.

Abstract: A first programmable device comprises non-dedicated, programmable resources including programmable logic; dedicated circuitry; a Joint Test Action Group (JTAG) interface adapted to selectively interchange signals with the programmable logic via the dedicated circuitry; and a Serial Peripheral Interface (SPI) interface adapted to (1) selectively interchange signals with the programmable logic via the dedicated circuitry and (2) selectively interchange signals with the JTAG interface via the dedicated circuitry. The JTAG interface is adapted to be connected to a first external device. The SPI interface is adapted to be connected to a second external device. The first programmable device is adapted to transfer signals from the first external device to the second external device via the JTAG interface, the dedicated circuitry, and the SPI interface without relying on any of the programmable resources.

Abstract: Pre-distortion, whose magnitude—and preferably phase—are frequency-dependent, is applied to a non-baseband input signal in order to reduce spurious emissions resulting from subsequent amplification of the signal. In preferred embodiments, the pre-distortion technique of the present invention is implemented in combination with the (frequency-independent) magnitude and phase pre-distortion technique described in U.S. patent application Ser. No. 09/395,490 (“the '490 application”), where the frequency-dependent pre-distortion corresponds to amplifier distortion that has a magnitude that is proportional to the frequency offset from the carrier frequency and a phase shift of ±90° on either side of the carrier frequency. Since these characteristics match those of a differentiator, a thorough correction of this part of the amplifier's distortion can be achieved using a differentiating circuit. Embodiments of the present invention may be implemented in the RF domain.

Abstract: In one embodiment of the invention, a programmable termination structure has first and second termination circuits for corresponding pads and a programmable connection therebetween. The first termination circuit supports first and second sets of termination schemes. A shared resistor is part of at least one termination scheme in each set. The first termination circuit supports a termination scheme between the first pad and a user-defined node connected to an on-chip capacitor such that first pad is connected via the termination scheme to the on-chip capacitor. Control circuitry automatically turns on and off a termination scheme for bidirectional signaling supported by the first termination circuit, wherein (1) the control circuitry turns off the termination scheme if an output buffer is configured to present outgoing signals at the first pad and (2) the control circuitry turns on the termination scheme if the output buffer is disabled in order to terminate incoming signals received at the first pad.

Abstract: In one embodiment of the invention, an address decoder for decoding a word-line address to energize a word line in a block of computer memory. Instead of relying on a distinct enable signal, a clock signal provides a reset function and an enable function to the address decoder. In one implementation, the address decoder includes negative-level-sense latches and 3-input AND gates to generate decoded address bits. Using the clock signal as one of the inputs to the AND gates ensures that all of the decoded address bits are 0 when the clock signal is low and that exactly one decoded address bit is 1 when the clock signal is high. In this way, the address decoder ensures that two or more word lines are not energized at the same time.

Abstract: A clock generator has a reset circuit and (at least) two dividers, where each divider divides a reference clock signal by a divisor value to generate an output clock signal. The reset circuit generates reset signals for the dividers, where the reset signals are delayed relative to one another by a selected number of reference clock cycles, such that the dividers generate output clock signals having a desired phase offset between them.

Abstract: An input signal is pre-distorted to reduce spurious emissions resulting from subsequent signal amplification. Frequency-dependent pre-distortion is preferably implemented in combination with frequency-independent pre-distortion, where the frequency-dependent pre-distortion corresponds to amplifier distortion that has a magnitude that is proportional to the frequency offset from the carrier frequency and a ±90° phase shift on either side of the carrier frequency. The frequency-dependent pre-distortion is generated by differentiating waveforms corresponding to two different sets of pre-distortion parameters with respect to time. In one embodiment, one of the differentiated waveforms is applied to a positive-frequency filter and the other to a negative-frequency filter to generate positive- and negative-frequency pre-distortion signals, respectively, to account for asymmetries in the amplifier characteristics. In another embodiment, only one of the differentiated waveforms is applied to an asymmetric filter (i.

Abstract: A frequency-dependent phase pre-distortion technique is applied to an input signal in order to reduce spurious emissions resulting from subsequent amplification of the signal. In preferred embodiments, the frequency-dependent phase pre-distortion of the present invention is implemented in combination with the (frequency-independent) magnitude and phase pre-distortion technique described in U.S. patent application Ser. No. 09/395,490 (“the '490 application”), where one or more frequency-dependent phase pre-distortion signals are either advanced or delayed relative to the main pre-distorted signal generated in accordance with the '490 application. Each frequency-dependent phase pre-distortion signal is preferably based on a 180° phase difference between a pair of (critical) frequencies located outside (e.g., one on each side) of the signal channel.

Abstract: In certain embodiments, the present invention is a word-line driver for an address decoder that decodes a multi-bit address to enable access to a row of circuit elements such as memory cells in a block of memory implemented in a dedicated memory device or as part of a larger device, such as an FPGA. The word-line driver has a feed-back latch for each word-line that ensures that the word-line is not energized when that word-line is not selected for access. By controlling the feed-back latch using a decoded address bit value rather than a pre-charged enable signal as do some prior-art dynamic word-line drivers, the word-line driver prevents undesirable energizing of multiple word-lines. The word-line driver can be implemented using less layout area and less power than some analogous prior-art static word-line drivers.

Abstract: An integrated circuit having a transistor device and over-voltage protection circuitry. The transistor device is implemented in a technology having a specified operating-voltage range, the transistor device having gate, drain, source, and tub nodes, and the specified operating-voltage range having a specified maximum voltage. The over-voltage protection circuitry is adapted to apply gate and tub voltages to the gate and tub nodes, respectively. If at least one channel voltage applied to at least one of the drain and source nodes exceeds the specified maximum voltage, then the over-voltage protection circuitry controls at least one of the gate voltage and the tub voltage to inhibit one or more adverse effects to the transistor device.

Abstract: An electrical system has a master circuit and an interface (I/F) circuit. The master circuit generates a master output signal. The I/F circuit receives an I/F input signal and a flag signal and generates an I/F output signal for application to a slave circuit, wherein the I/F input signal is based on the master output signal, and the interface circuit generates the L/F output signal either dependent on or independent of the I/F input signal as indicated by the flag signal.

Abstract: A buffer for a programmable device has source current circuitry, sink current circuitry, one or more input nodes, one or more output nodes, and switch circuitry. The source current circuitry can be programmably controlled to generate a plurality of different total source currents, and the sink current circuitry can be programmably controlled to generate a plurality of different total sink currents. The one or more input nodes can receive one or more input signals, and the one or more output nodes can present one or more output signals. The switch circuitry can selectively apply at least one of a total source current and a total sink current to the one or more output nodes based on the one or more input signals.

Abstract: Pre-distortion, whose magnitude—and preferably phase—are frequency-dependent, is applied to an input signal in order to reduce spurious emissions resulting from subsequent amplification of the signal. In preferred embodiments, the pre-distortion technique of the present invention is implemented in combination with the (frequency-independent) magnitude and phase pre-distortion technique described in U.S. patent application Ser. No. 09/395,490 (“the '490 application”), where the frequency-dependent pre-distortion corresponds to amplifier distortion that has a magnitude that is proportional to the frequency offset from the carrier frequency and a phase shift of ±90° on either side of the carrier frequency. Since these characteristics match those of a differentiator, a thorough correction of this part of the amplifier's distortion can be achieved using a differentiating filter. Embodiments of the present invention may be implemented in the baseband domain.

Abstract: In one embodiment of the invention, a block of configuration memory has rows of memory cells, at least one row having a set of one or more dual-port memory cells adapted to selectively store either configuration data or local data. The configuration address line for that row is segmented such that the address line is connected to the configuration address ports of the dual-port memory cells via access control circuitry that can be programmably configured to prevent access to those memory cells via the configuration address line. The access control circuitry enables local data to be efficiently and accurately stored in the dual-port memory cells without interference from configuration readback operations during normal operation or from partial reconfiguration of the configuration memory.

Abstract: Two or more microphones receive acoustic signals and generate audio signals that are processed to determine what portion of the audio signals result from (i) incoherence between the audio signals and/or (ii) audio-signal sources having propagation speeds different from the acoustic signals. The audio signals are filtered to reduce that portion of one or more of the audio signals. The present invention can be used to reduce turbulent wind-noise resulting from wind or other airjets blowing across the microphones. Time-dependent phase and amplitude differences between the microphones can be compensated for based on measurements made in parallel with routine audio system processing.