Abstract: An apparatus and method for programmable lock detection and correction (PLDC) to a programmable accuracy in a digital delay-locked loop (DLL) based multiphase clock generator (MCG) is based on a DLL that utilizes a digital count to control the delay of a digitally controlled, multiple-tap delay line in its feedback path where stability of the digital count is used to qualify the determination of lock to a programmable accuracy and lock determination is based on combinatorial evaluation of the multiple phase outputs for the proper waveform relationships. The incidence of false lock corresponding to excessive delay through the delay line is addressed by a LOOPRESET signal that results in a reset of the digital count that controls the delay through the delay line. Additionally, programmability of the stability interval, the digital counter step size, and the accuracy of the lock provide control over lock acquisition time.

Abstract: Current and previous input signal power measures are used to generate a combined index value that is applied to one or more composite look-up tables (e.g., an I LUT and a Q LUT) to retrieve one or more pre-distortion parameters (e.g., I and Q). In one embodiment, a combined index value is generated by concatenating current and previous power measures, where each composite LUT maps all possible combinations of the current and previous power measures to the corresponding pre distortion parameters values. By using a composite LUT for each of I and Q, the overall signal processing time of the pre-distortion processing can be greatly reduced relative to the prior art, resulting in a significantly smaller RF delay line used to delay the input signal and thereby providing a less costly and more efficient amplifier system.

Abstract: A programmable logic device (PLD), such as a field programmable gate array (FPGA) has a logic core surrounded on one or more sides by an input/output (I/O) interface having one or more programmable I/O buffers (PIBs). At least one PIB can be programmed to perform two or more of (a) a pass-through data input mode, (b) an input register mode; (c) a double data rate (DDR) input mode, (d) one or more demux input modes, (e) one or more DDR demux input modes. In addition or alternatively, at least one PIB can be programmed to perform two or more of (a) a pass-through data output mode, (b) an output register mode, (c) a DDR output mode, (d) one or more mux output modes, and (e) one or more DDR mux output modes. As such, devices of the present invention are flexible enough to support both low-rate and high-rate interface applications, while efficiently using device resources.

Abstract: The input and output of amplifier (110) are sampled and downconverted in frequency and filtered at (124 and 126) to produce sub-band signals. The input signal sub-band (134) is then subtracted from the output signal sub-band (136) at (130) to produce a residual signal (132) containing any distortion present in the sub-band selected by the downconversion oscillator (128). Signal analyser (158) compares the input and output signal energy to deduce the amount of distortion in the output signal, to provide signals for controlling a distortion reduction mechanism such as a predistorter operating on amplifier (110). Alternatively, the input signal sub-band (134) and the output signal sub-band (136) are Fourier transformed (210 and 212) to produce spectrums which can be analysed to determine the presence of distortion in the output of amplifier (110).

Abstract: A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).

Abstract: A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).

Abstract: A capacitor cancellation method and apparatus for use in an interface circuit having a transformer blocking capacitor. The method includes sensing a voltage across the transformer blocking capacitor and generating a cancellation signal to compensate for the effect of the transformer blocking capacitor. The apparatus includes a sensor to sense a differential voltage across the transformer blocking capacitor to develop a capacitor signal and an amplifier to amplify the capacitor signal to obtain a cancellation signal.

Abstract: An input signal having amplitude information is pre-distorted and converted into two pre-distorted signals without amplitude information. The two pre-distorted signals are separately amplified and then recombined to generate a linearized amplified output signal having amplitude information. The pre-distortion and conversion may be implemented using a pre-distorter and a LINC modulator. Alternatively, the pre-distortion and conversion may be implemented in circuitry that combines the functions of a pre-distorter and a LINC modulator. The amplified, pre-distorted signals are preferably combined using circuitry that provides at least some impedance matching, such as a transformer or a transmission line tee with transmission line stubs.

Abstract: A folded cascode device senses the drain current of a source follower, and a current mirror device multiplies the sensed drain current for application to an output load. The source follower and the current mirror device are preferably of the same type (e.g., both NMOS). The resulting composite source follower provides relatively wide bandwidth at relatively low power. The folded cascode allows (NMOS) source and sink control. Using current mirror feedback reduces the stability problems associated with other solutions that rely on a voltage feedback stage. Composite source followers of the present invention can be used in any traditional buffer applications, such as in operational amplifiers, regulators, or high-speed signal paths.

Abstract: A termination scheme for the I/O circuitry of a programmable device, such as a field-programmable gate array (FPGA), has programmable resistors switchably connected between reference voltages and two of the device's I/O pads and additional programmable resistors switchably connected between the two I/O pads. By appropriately controlling the reference voltages and the resistance levels, a single implementation of the termination scheme can be used to conform to a relatively wide variety of symmetric and non-symmetric complementary and differential signaling applications.

Abstract: A subscriber-line interface circuit (SLIC) has tip and ring amplifiers connected to the tip and ring lines, respectively, of customer premises equipment (CPE). The SLIC returns the ringing signal (provided to the CPE from a power supply connected to the CPE's ring line), to ground or to battery, through the SLIC's tip amplifier. In one embodiment, the SLIC has three switches: S1 connecting the power supply to the ring line, S2 connecting the ring amp to the ring line, and S3 connecting the tip amp to the tip line. During ringing, S1 and S3 are closed to return the ringing signal to ground through the tip amp, which is preferably driven to saturation during ringing to reduce power consumption. By eliminating the fourth switch that appears in prior-art SLICs (e.g., connecting the tip line to ground), SLICs of the present invention can be smaller and therefore less expensive to implement.

Abstract: A power amplifier's complex pre-distortion curve is generated by decomposing a representation of an input signal, processing the resulting decomposed signals using analog techniques, and performing signal re-composition. In one implementation, two different halves of a transfer function corresponding to the amplitude characteristics of the amplifier are separately modeled and then combined to generate a control signal used to control a voltage-controlled attenuator that attenuates the input signal, while two different halves of a transfer function corresponding to the amplifier's phase characteristics are separately modeled and then combined to generate a different control signal used to control a voltage-controlled phase shifter that adjusts the phase of the input signal. The resulting output signal corresponds to an amplitude-and-phase pre-distorted signal that can be applied to linearize a corresponding (high power) amplifier.

Abstract: Multiple product terms (PTs) are combined with a multiple-input look-up table (LUT) to form a LUT-based Boolean term (LBT) that generates a Boolean output. Multiple LBTs are combined with one or more sum terms to form an enhanced generic logic block (EGLB) that can be programmed to operate, e.g., as a sum-of-products structure, where the EGLB structure can be repeated within a programmable logic device (PLD). Different multi-bit Boolean functions can be implemented in a single pass through each EGLB, with fewer resources then prior art structures. Multiple LBTs can be combined with other logic to form combined LBTs (CLBTs). This invention can provide improved Boolean function packing density compared to existing PLD architectures and/or shorter delays for a comparable packing density.

Abstract: A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.

Abstract: The insertion phase or delay of an amplifier can be controlled by comparing signals from the amplifier path with signals from a corresponding reference path without requiring the overall signal delay through the reference path to nominally match the overall signal delay through the amplifier path. Amplifier and reference path signals can be combined to form a combined signal whose power is detected using a narrow-band, frequency-selective power detector. For given phase and delay offsets between the amplifier and reference paths, cancellation (i.e., perfectly destructive interference) will occur at a series of different frequencies. By operating the power detector at one of these cancellation frequencies, a variable phase or delay adjuster in the amplifier path can be controlled to minimize the detected power level in order to achieve a desired level of insertion phase for the amplifier, without having to implement an expensive delay element in the reference path.

Abstract: A signal to be amplified is provided in polar format comprising an amplitude component (210) and a phase component (212). The amplitude component (210) is used to bias the phase component (212). The gain of amplifier (220) depends upon the bias of the signal that it receives. Therefore, the bias given to the phase component (212) provides the envelope characteristics of the output signal (224) of amplifier (220). Both (or either) of the amplitude component (210) and the phase component (212) may be predistorted (226, 310) to eliminate distortion appearing in the output signal (224).

Abstract: A circuit is provided where impedance converters (41-48) are provided such that active components (P1 to P8) can be switched off without power from the other active components leaking away through those components which are switched off.

Abstract: An impedance warping circuit (IWC) and technique for compensating the effect of a blocking capacitor within a transformer of an interface circuit for passing plain old telephone service (POTS) band and asynchronous digital subscriber line (ADSL) band signals on signals having frequencies in the POTS band. The IWC does not significantly affect the performance of the interface circuit in the ADSL band. The IWC synthesizes impedance to compensate the frequency-dependent deviation in the termination impedance across the tip/ring lines. The resulting termination impedance may be designed to conform to the Telcordia Standard of 900 ?+2.16 ?F or other telecommunication standards throughout the entire POTS band.

Abstract: Limiting amplifier (116) removes amplitude variations from the input signal (110). Splitter (120) provides the constant amplitude signal to each of amplifiers (124A to 124H) via a respective switch (122A to 122H). The envelope of the input signal (110) is detected at (134) and digitized at (138). The bits of the digitized envelope signal are used to control switches (122A to 122H). The output ratings of amplifiers (124A to 124H) form a series wherein each successive output rating is twice the preceding one. Thus, the bits of the digitized envelope signal can be used to reconstruct the envelope of the output signal provided by combiner (126). Several of the amplifiers may be replaced by a single amplifier to simplify the circuit (210, FIGS. 2 and 3). The input signal may be digital removing the need for envelope detection (FIG. 4). Errors in the output may be compensated using a feedback mechanism (FIGS. 5 and 6).

Abstract: A method for placing configurable logic blocks (CLBs) in a PLD, such as an FPGA. In one embodiment, after packing gates/clusters into blocks and then assigning those blocks to CLBs to generate an initial placement, the packing and/or placement of CLBs is changed prior to performing CLB routing. For each node of the most critical of the K most critical paths in the initial placement, moving the node to a different CLB is considered in order to reduce the criticality of that path. A move is applied if certain acceptability conditions are met. After the most critical path is improved, the criticality of the K paths is updated, and the procedure is repeated for the new most critical of the K updated paths. The method, which can be automated to reduce human intervention in the design process, improves circuit performance, e.g., by enabling higher circuit operation frequencies.