Abstract: A phase-locked loop (PLL) having a digitally controlled oscillator (DCO), where the DCO receives a digital control signal generated by the PLL and an externally generated oscillator clock signal and generates an output signal having a frequency greater than that of the oscillator clock signal. In one embodiment, the DCO is an analog PLL, such as a fractional-N frequency synthesizer, that receives a two-part digital control signal corresponding to the integer and fractional portions of a desired multiplier. The feedback path within the DCO has a dual-modulus divider that is controlled by a modulus controller to apply, over time, an effective divisor value that achieves the desired degree of multiplication. PLLs of the present invention are especially applicable to low-bandwidth, low-noise applications, such as high-multiplication frequency synthesizers and clock filtering, that are integrated into digital ASICs.

Abstract: A two-step training method for the estimation filter in the echo cancellation (EC) path of the analog front-end (AFE) circuit for a modem, such as an asymmetric digital subscriber line (ADSL) modem. During the first step, the coefficients of a filter that is preferably equivalent to the combination of the EC path and the receive (RX) path in the AFE circuit are determined with the EC estimation filter held fixed and the transmit (TX) path in the AFE circuit disabled. During the second step, the TX path is enabled and the coefficients of the EC estimation filter are determined using the path equivalent filter generated during the first step. The two-step training method takes into account variations in the operating characteristics of components in the various processing paths in the AFE circuit to converge on satisfactory coefficients for the EC estimation filter within an acceptable number of training symbols.

Abstract: The lineariser (1) comprises a digital signal processor (DSP) (100) for reducing distortion of the output of non-linear RF power amplifier (200). The DSP (100) implements a predistorter process (102) which predistorts the input to amplifier (200) in such a manner as to counter distortion imposed by the amplifier. Feedback from the amplifier output is sampled at (212) to provide a feedback signal for controlling the predistortion process. Additionally, a feedforward signal is combined with the amplifier output at (216) to further reduce distortion therein. The feedforward signal is derived by subtracting the input signal, at (112), from feedback from the output of amplifier (200) (which may contain residual distortion). The vector modulator (114) conditions the result of the subtraction process (112) to produce the feedforward signal.

Abstract: A shared data and clock recovery circuit including a clock synthesizer for generating sampling signals having different phases, a multiple transition detector for receiving a data stream and sampling signals, and for detecting edges in a data stream in response to the sampling signals, a counter and accumulator for detecting the time occurrences and total number of edges, and for performing weighted average calculation to select one of the phases, a decision circuit for detecting the phase difference between a source clock and a local clock such that if the PPM difference between the source clock and the local clock is at least 200 PPM, then selection of a phase is based upon stored historical information, and if the PPM difference between the source clock and the local clock is less than 200 PPM, then selection of a phase is based on a weighted averaging calculation.

Abstract: A second-order adaptive differential microphone array (ADMA) has two first-order elements (e.g., 802 and 804 of FIG. 8), each configured to convert a received audio signal into an electrical signal. The ADMA also has (i) two delay nodes (e.g., 806 and 808) configured to delay the electrical signals from the first-order elements and (ii) two subtraction nodes (e.g., 810 and 812) configured to generate forward-facing and backward-facing cardioid signals based on differences between the electrical signals and the delayed electrical signals. The ADMA also has (i) an amplifier (e.g., 814) configured to amplify the backward-facing cardioid signal by a gain parameter; (ii) a third subtraction node (e.g., 816) configured to generate a difference signal based on a difference between the forward-facing cardioid signal and the amplified backward-facing cardioid signal; and (iii) a lowpass filter (e.g.

Abstract: An iterative decoder employs detection and post-processing of channel output samples to generate soft output vales for encoded data provided to the decoder for one or more iterations of decoding. The channel output samples account for user data encoded with concatenated codes. For one or more other iterations, the reliability values of the soft values of the prior iteration are updated, generating soft output data for the decoder for the current iteration of decoding. A detector may use a soft-output Viterbi algorithm (SOVA) to detect encoded data from channel output samples, and the SOVA algorithm may be implemented by a Viterbi algorithm generating hard decisions from the output channel samples followed by post-processing to generate and update reliability values for the soft-output values based on the hard decisions and output channel samples.

Abstract: A process for evaluating and correcting virtual integrated circuit designs includes a method and apparatus for determining a ratio of an amount of material, i.e. polysilicon or metal, in any given layer to an area of the layer. The ratio is then compared to a predetermined target ratio, which is based on a ratio of the total amount of the material to the entire area of the I-C design. The process then automatically inserts or deletes an amount of material from the layer as needed, using any of four methods. These methods include deletion, scaling, deletion and scaling or striping. The ratio for an erroneous layer is rechecked after the first correction is performed and the entire process is repeated using a Newton-Raphson or a Least Absolute Deviation Regression method until the ratio falls within the predetermined tolerances. If the layer has been filled, the layer is further checked for short circuits, fill isolation violations, antenna violations and the like which may have resulted from the material fill.

Abstract: An improved method and apparatus for connecting various function modules located within a computer or communications system are proposed. In accordance with the principles of the present invention, a port manager controller (PMC) has a direct interface to each of the function modules and to a host component such as a system memory or a CPU. The PMC replaces both the local bus and the arbitrator of prior art systems. All the requests by function modules to access the host component are first processed by the PMC. The PMC schedules the incoming requests in accordance with predefined parameters, such as priority, efficiency, and/or timing. The PMC is capable of handling more than one request at a time. The PMC is also capable of dynamically adapting to load conditions and rearranging the incoming requests to efficiently utilize the available bandwidth. Thus, the PMC reduces latency and improves the performance of the computer or communications system.

Abstract: A data transmission system employs an iterative decoder that applies decision feedback equalization (DFE) to channel output samples of a packet of data. The iterative decoder receives a stream of channel output samples as packets that may, for example, be read from a sector of a recording medium. Each packet may represent user data encoded, for example, with a concatenated code formed from N component codes, N a positive integer. The iterative decoder employs I decoding iterations, I a positive integer. DFE employs two filters: a feedforward filter and a feedback filter. The feedforward filter, which may be a whitened-matched filter used for detection, shifts dispersed channel output energy into the current sample. The feedback filter cancels energy of trailing inter-symbol interference from previous symbols.

Abstract: A phase-modulated signal such as a quadrature phase-shift-keyed (QPSK) signal in a wireless communication system is demodulated by frequency demodulating the phase-modulated signal. The phase-modulated signal is separated into first and second copies, the first copy is phase demodulated to generate demodulated symbols, and the second copy is frequency demodulated to generate, e.g., a measure of the instantaneous frequency of the phase-modulated signal. The instantaneous frequency measure is processed to identify one or more symbol transitions, and the identified transitions are used to generate event signals having signature properties (signature events). These signature events are used in traditional Time Difference of Arrival tdoa algorithms to accurately determine position of a mobile unit in the wireless communication system.

Abstract: An offset sequence generator generates an offset sequence from a reference sequence, the offset sequence being a cyclic-shifted version of the reference sequence. The reference sequence is a deBruijn sequence formed from a pseudo-noise (PN) sequence augmented with an insert-bit, the insert-bit being inserted at a rollover state of the PN sequence. The offset generator includes a decision circuit that selects values of either the reference sequence or a delayed reference sequence as an input to a mask circuit. The mask circuit applies masks so as to generate the PN sequence of the offset sequence. The decision circuit also detects the rollover state of the PN sequence of the offset sequence, and inserts the insert-bit so as to provide the offset sequence.

Abstract: An interleaver generates a valid interleaved data address for each iteration i of the mapping by the interleaver without employing a multiplication operation. The interleaver includes an address generator comprises two counters, bit-reverse and index tables, and an accumulation register array. The interleaver further comprises two adders, two registers storing tentative address values addressi and addressi+1, and select logic including a comparator, two buffers, and a multiplexer (mux). Two counters are employed to allow the interleaver to generate at least one valid address for each iteration, and a tentative address is generated from each output value of the two counters. Each iteration generates an output interleaved address. A tentative address is generated by using a portion of the counter value as an address to select a corresponding entry from each of the bit-reverse and index tables and the accumulation register array.

Abstract: The present co-synthesis technique takes as an input embedded system specification in terms of acyclic task graphs, system constraints, and a resource library consisting of several functional blocks such as processor cores, memory, proprietary and non-proprietary functional blocks, and generates a low-cost hardware and software architecture for systems-on-a-chip such that all real time constraints are met while minimizing average power dissipation. It employs a floor-planning based delay estimator during evaluation of various architectures. Actual delay measurements made on synthesized chips indicate that the delay estimator error is less than 12%. The technique can be extended to derive fault-tolerant architectures for systems-on-a-chip employed in critical applications. Fault-detection capability is imparted to the system by adding assertion and duplicate-and-compare tasks to the task graph specification prior to co-synthesis. Error recovery is achieved by switching to spare functional blocks.

Abstract: Photo-sensors, such as photo-diodes, are formed using regions with cross-sections that increase the overall quantum efficiency of the resulting photo-sensor. The cross-sections have additional (e.g., interior) side-wall interfaces, and, in some embodiments, an additional, relatively shallow bottom interface. The increased total side-wall area and any additional shallow bottom area increase the total photo-junction volume located near the surface of the device. As a result, a greater fraction of photons having relatively small absorption lengths (e.g., blue light) will be absorbed within a photo-junction, thereby increasing the quantum efficiency for those photons. The present invention enables photo-sensors to be implemented with more uniform spectral response.

Abstract: A circuit and method for equalization of a communication signal received over a communication system transmission line using switched filter characteristics. Equalization for frequency-independent and frequency-dependent attenuation of the communication signal is accomplished with a linear equalization channel which includes an input biasing circuit which provides a common input signal to two parallel amplifier paths. One path includes a wideband, fixed-gain, frequency-independent amplifier stage. The other path is a wideband multiplier amplifier stage in series with a wideband, frequency-dependent amplifier stage having a switchable high-pass characteristic. The outputs of the fixed-gain wideband frequency-independent amplifier stage and wideband, frequency-dependent amplifier stage having a switchable high-pass characteristic are both tied in common to the input of a wideband gain buffer amplifier stage, which has a switchable high-frequency boost frequency response characteristic.

Abstract: A system is disclosed that services a plurality of queues associated with respective data connections in a packet communication network such that the system guarantees data transfer delays between the data source and the destination of each data connection. This is achieved in two stages. The first stage shapes the traffic of each connection such that it conforms to a specified envelope. The second stage associates timestamps with the packets released by the first stage and chooses for transmission from among them the one with the smallest timestamp. Both stages are associated with a discrete set of delay classes. The first stage employs one shaping structure per delay class. Each shaping structure in turn supports a discrete set of rates and employs a FIFO of connections per supported rate. A connection may move between FIFOs corresponding to different rates as its rate requirement changes.

Abstract: In a system that has a redundant pair of modules where one module is the active module and the other module is the standby module, each of the two modules includes equipment such as an inexpensive programmable logic device to provide a protection switching algorithm for determining, at the individual module level, whether a module is in the active or standby state and switching a module from a standby state to its active state when the module in the active state becomes defective. The number of wires that are required as module to module indicators is reduced to two. The processor can make the active, standby determination when the two modules are powered up simultaneously, when one module is inserted subsequent to the other, or where a module has been active and then fails or is unexpectedly removed.

Abstract: A phase-locked loop (PLL) employs a ring oscillator for the voltage-controlled oscillator (VCO), and the ring oscillator comprises an odd number of inverting stages operating at a given frequency. The frequency of the ring oscillator is determined by the delay through each stage and the number of stages. The output signal of each stage has a phase determined by the number of stages, and each stage provides its output signal with a different phase. The VCO of the PLL selects phases of the ring oscillator to clock the counter of the feedback divider of the PLL. Each phase is selected by a multiplexer (mux) under the control of a finite state machine that monitors the output of the counter. When the counter completes a full count cycle on one phase of the ring oscillator, the finite state machine selects a different phase of the ring oscillator to clock the counter for the next count cycle.

Abstract: An iterative decoder decodes a frame of encoded data that includes error detection information, and terminates the iterative decoding based on a comparison of the decoded frame with the error detection information. The iterative decoder may have a maximum number of specified iterations, but may terminate the number of iterations early under specified conditions. The encoded data includes error detection information for parity check calculation. Error detection information may be in accordance with an error detection code, such as a cyclic redundancy check (CRC) code. After each iteration of decoding, a parity check is calculated for the decoded frame. Early termination of decoding may occur prior to an intermediate iteration threshold M of iterations when the parity check value of the decoded frame is equivalent to the parity check value calculated from the error detection information.

Abstract: A duobinary modulator and a method of modulating an optical signal so as to be coded in a duobinary manner, using optical modulating specifically adapted for this purpose is provided. Two input electrical signals are respectively input to two binary encoders. The binary encoders encode the input electrical signals and generate a pair of encoded binary signals which are then input to an analog amplifier. The analog amplifier amplifies the encoded binary signals and generates a pair of duobinary signals. Then, the duobinary signals are input to a dual-electrode modulator which modulates a pair of optical beams with the duobinary signals to generate a pair of modulated optical duobinary signals. Both modulated optical duobinary signals are then combined to generate the desired high-speed modulated optical duobinary signal.