Abstract: An iterative decoding system for intersymbol interference (ISI) channels has a module for extracting bit reliabilities from a partial response (PR) channel, an iterative decoder, and a module for updating the bit reliabilities. A transmitter parses a data sequence into blocks that are encoded to generate a sequence of codewords. By encoding, a correlation among the bits of each codeword output to the PR channel is created. A maximum likelihood sequence detector (MLSD) in the receiver produces estimates of transmitted bits from samples of the output from the PR channel. The MLSD detector has a priori knowledge of typical error events that can occur during transmission through the channel. Along with the bit estimates, at each time instant the MLSD detector generates set of error event likelihoods.

Abstract: A first transceiver transmits a set of test levels to a second transceiver through a communication channel with one or more types of companding laws. The second transceiver determines line encoding with, and conversion between, the companding laws present in the communication channel based on the received set of test signals. The set of test levels are signals having levels determined based on the difference between the normalized amplitude, vertex, or energy curves for the types of companding laws, with or without accounting for other sources of network distortion. Additional distortion from line characteristics, such as robbed-bit signaling (RBS) and/or line impairment, may be detected based on changes in encoding sample levels of transmitted test signals that are reconstructed by the second transceiver. The second transceiver may then transmit information to the first transceiver about the companding laws and other sources of distortion present in the network.

Abstract: Solar water heaters may include a solar collector in a decorative structure, and solar collectors comprising a coil of tubing are adapted to be disposed in a decorative structure such as a wishing well. In one embodiment, a solar water heating system comprising a decorative structure and a coil of tubing disposed within the decorative structure, the coil having a helical shape and being oriented with its axis disposed generally vertically. In another embodiment, a method comprises the steps of providing a coil of tubing, the coil having an axis and the tubing of the coil being radially spaced from the axis; disposing the coil in a location receiving sunlight with the coil axis oriented generally vertically; and causing fluid to flow through the coil.

Abstract: An OAUGD plasma is generated using, for example, paraelectric or peristaltic electrohydrodynamic (EHD) techniques, in the plasma generator of a remote-exposure reactor, wherein one or more active species, especially oxidizing species in the plasma are convected away from the plasma-generation region and directed towards a workpiece that is located outside of the plasma-generation region (e.g., within an optional remote-exposure chamber configured to the plasma generator). In this way, the workpiece can be subjected to the one or more active species without directly being subjected to either the plasma or to the electric fields used to generate the plasma. The plasma generator may have a set of flat panels arranged within an air baffle to convect the active species in a serpentine manner through the plasma generator.

Abstract: A method for synchronizing multi-carrier signals in an orthogonal frequency division modulation (OFDM) data transmission system is disclosed which provides maximum likelihood estimation of timing offset and frequency offset. The estimates are able to compensate the estimation error over an entire span of observed data samples. The method requires no training sequence thus enabling blind frequency compensation. The method provides a joint probability density function for the estimates which consists of two terms; one generated from observed data received during a first interval and one generated from observed data received during a second, following, interval. The estimates provided by the method are therefore maximal likelihood over the entire span of observed signals and are a significant improvement over estimates provided by methods based only observations during the first interval. The method is mathematically robust and computationally and statistically efficient.

Abstract: An amplifier having an improved output current drive capability includes an input stage and an output stage. An input of the output stage is operatively coupled to an output of the input stage. The amplifier further includes a current regeneration circuit operatively coupled to the input of the output stage in a feedback arrangement, the current regeneration circuit feeding back a current to the output circuit in accordance with a predetermined scale factor, the fed back current being proportional to an input current supplied to the output stage. The input current supplied to the output stage is dynamically adjustable by the current regeneration circuit in response to an input current requirement at the output stage.

Abstract: Single-bit-timestamp discrete-rate scheduling distributes service to competing connections (e.g., packet connections such as virtual-circuit connections) using a single bit for each connection, rather than using one or more multi-bit timestamps per connection. Single-bit timestamps are computed and sorted for scheduling packets in, for example, Asynchronous Transfer Mode (ATM) networks, for guaranteeing data transfer rates to data sources and data transfer delays from data sources to destinations. Connections are listed in one of N first-in, first-out (FIFO) rate queues j, each rate queue j, 1≦j≦N, associated with one of N service rates. A scheduler identifies the next connection for service as the connection VCj,i being at the head of the rate queue with the minimum corresponding timestamp among those rate queues having timestamps satisfying an eligibility condition.

Abstract: A system employs a modified Jakes' fading model to generate a fading signal having substantially equivalent autocorrelation values for in-phase (I) and quadrature-phase (Q) components. A Walsh transform may be applied to generate multiple, uncorrelated I and Q components, for multiple fading signals. A complex Rayleigh fading signal according to the modified complex Jakes fading model is provided by a generator having M pairs of I and Q paths. Each pair of I and Q paths includes a corresponding complex carrier generator 201 (M an integer and 1≦n≦M) generating a complex carrier signal with frequency, &ohgr;n, where &ohgr;n is cos ((4n−3&pgr;)/4M). Each of the I paths has a circuit that separates the real component of the corresponding carrier signal to provide a real carrier signal cos (&ohgr;nt). Similarly, each of the Q paths has a circuit that separates the imaginary component of the corresponding complex carrier signal to provide an imaginary carrier signal sin (&ohgr;nt).

Abstract: A circuit performs threshold normalization of accumulated transition probabilities for a given state of a state transition trellis in a maximum likelihood detector. Threshold normalization may be accomplished by comparison and setting of a single bit in stored transition probabilities. Threshold value comparison may be accomplished by comparing the bth bit of the stored transition probabilities if the threshold value is 2b. When all transition probabilities exceed the threshold value at a stage of the trellis, the transition probabilities are scaled, such as by subtracting the threshold value. Scaling may be implemented by setting the compared bth bits to zero before storage. In general, since accumulated transition probabilities are monotonically increasing for transition probabilities of paths through the trellis in both forward and reverse directions, the present invention may be employed for both threshold normalization of both the forward (&agr;) and reverse (&bgr;) transition probabilities.

Abstract: A controller for residential telephone wiring. Apparatus associated with the controller provides multiple communication channels on ordinary residential telephone wiring. The controller (1) routes incoming calls to a selected telephonic device within the residence, (2) routes outgoing calls to a free external line servicing the residence, and (3) routes calls within the residence from one telephonic device to another.

Abstract: An automatic gain control (AGC) system controls a receiver having multiple amplifier stages with near constant compression. The AGC system controls gain, and thus compression, of each stage employing information generated by the other stages to generate feedback signals at a system level. A central controller uses threshold detection to monitor signal power at each stage of the receiver signal path as well as overall signal gain. Based on these various signal power measurements, the central controller adjusts signal gain of the input to one or more stages, while maintaining overall signal gain for a constant output signal level. The AGC function may be implemented by switching the gain of each stage's variable amplifier in discrete steps in discrete steps, with the step size being coarser for stages closer to the input signal than those closer to the final output baseband signal.

Abstract: An iterative decoder limits the range of extrinsic information used for iterative decoding of an encoded frame of data. The iterative decoder includes two or more separate decoders for decoding a received encoded frame of data. Each decoder employs extrinsic information generated from the soft data generated by another decoder decoding the encoded frame of data. The extrinsic information includes an approximate measure of the probability that a particular transmitted bit received by the iterative decoder is a logic 0 or logic 1. The extrinsic information for the bit originates with one decoder and is used by another decoder as external information about that bit. Implementations of the iterative decoder use saturation values to define the boundaries of the range. The saturation values are selected such that either no or relatively small degradation in BER occurs, and the saturation values also define the width of the binary representation of the extrinsic information.

Abstract: A recurring noise filter for removing from a signal noise generated by parasitic coupling from a switching network. The filter contains an input filter, a sampling switch and an output filter. The input filter is a low pass filter which receives a signal containing noise generated by parasitic coupling from a switching network. The sampling switch is connected between the low pass filter and an output filter, with the sampling switch activating in response to the recurring switching of said switching network to sample the signal during the interval at which said noise does not occur within the signal. The output filter removes signals generated by the sampling switch from the sampled signal thereby generating a noise-filtered signal.

Abstract: A set of orthogonal sequences (e.g., Hadamard sequences) is decomposed into a set of basis vectors and sets of coefficients, where each set of coefficients represents a particular “vector combination” of the basis vectors that forms one of the orthogonal sequences. Such decomposition of orthogonal sequences into basis vectors and sets of coefficients may allow for a reduction in memory space and/or processing required to generate one or more of the orthogonal sequences during real-time operations of a communications system, such as an IS-95 CDMA system, that employs the orthogonal sequences. In one embodiment, a Hadamard sequence generator includes a controller, a memory, and a combiner. The set of basis vectors are stored in the memory, and each of the Hadamard sequences has a corresponding set of coefficients from which the Hadamard sequence can be derived as a vector combination of the basis vectors.

Abstract: An apparatus and method of a shared correlator system for a code division, multiple access (CDMA) receiver employs scheduling of correlation operations with identification tags (ID-tags). The scheduling allows for shared vector generation and correlation operations between processing units by pipeline processing. The shared correlator schedules correlation operations requested by processing units, generates matched-filter PN vectors associated with the identification tags for the correlation operations, and provides correlation results for the correlation operations. Scheduling may be implemented with a control processor, scheduler and memory. The control processor determines the matched-filter PN vector information for a requested operation using the current state of a reference PN code sequence, and this information is stored as the ID-tag. The control processor stores the ID-tag at an address in memory associated with a slot of a periodic symbol schedule.

Abstract: A system for block encoding and block decoding of servo data with a rate (M/N) code, where M is an integer greater than 1 and N is an integer that is greater than M. Two codes are described for the encoding and decoding processes: a rate (2/6) code and a rate (2/8) code. In general, block encoding and-block decoding maps between M servo data bits and N coded symbol bits. Such block encoding with a rate (M/N) code may be employed in a magnetic recording system for encoding servo data that is written to a servo data sector on a magnetic recording medium. Encoded servo data is read from the magnetic medium and block decoded. A forced maximum-likelihood, partial-response (PRML) detector is used to detect the N coded symbol bits from channel samples read from the magnetic medium. Block encoding provides greater coding gain for a detector when the characteristics of the block code are used to improve performance of the PRML detector that is used to detect the N coded symbol bits.

Abstract: A product code and interleaving/de-interleaving process are designed to work in combination to improve the coding gain of the product code. Such improvement of coding gain is based on an error constraint. The error constraint is a maximum number of values in error per block in the detected decisions for received output channel samples. The error constraint may be a burst error constraint, such as a maximum number of errors in a block introduced by burst noise in the communication channel; or the error constraint may be an error event constraint, such as the error event generated by an incorrect decision for a path through the trellis of the Viterbi algorithm employed by the detector or a combination of both. In one implementation, a block of data of length N is encoded with a product code of two dimensions with N a positive integer. The product code includes an error correcting capability of detection and correction by a receiver of single one-bit errors in the encoded block.

Abstract: A transmit portion of a WB-CDMA transceiver generates one or more spread data streams having values represented by a single bit, allowing for filtering of spread and combined data streams with a root raised cosine (RRC) filter employing single-bit multipliers. The RRC filter is a digital filter that i) employs multiplication of two values in which the length of at least one value is one bit; ii) is preferably implemented with muxs or a simple logic operator; and iii) may employ upsampling and modulation encoding of filter coefficients to reduce the coefficient length to, for example, one bit. The RRC filter may be an FIR filter having either one-bit or multi-bit coefficients, and apply RRC filtering to a spread user stream either before or after the spread user streams are combined. For some implementations, RRC filters are employed to filter each spread user stream prior to combining several processed user steams.

Abstract: This invention concerns a novel traceback memory management method and apparatus in which a memory stores Viterbi trellis state records and shifts the records in a manner so that the memory mirrors the relevant portion of the trellis accessed during the traceback for error correction and decoding. Several pointers are used so that a random access memory (RAM) can store and access the Viterbi trellis state records with only a minimum amount of hardware required to implement the memory accesses. In certain instances, where memory length is a power of 2, entire elements needed in the address generation steps are eliminated by the invention, thereby saving valuable chip area and clock cycles.

Abstract: In a transmitter circuit designed to operate over a specified transmit frequency range, information as to the specific frequency within the specified transmit frequency range at which the transmit up-converter of the transmitter circuit is to be operated, is used to generate a control signal for a high-power amplifier within the transmitter circuit, where the high-power amplifier automatically optimizes its operations based on the frequency indicated by the control signal. For example, for the transmitter circuit of a PCS base station transmitter, control signals received by the transmit up-converter from an alarm control board identify the particular 5-MHZ or 15-MHZ PCS frequency block for the base station transmitter. The up-converter uses that frequency information to generate a two-bit control signal identifying one of three 20-MHZ frequency sub-ranges within the 60-MHZ PCS forward-link transmit frequency range.