Abstract: A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.

Abstract: An improved signal detector system implementable in a high-speed SerDes receiver core that is able to detect valid signals from noise signals with a much tighter tolerance. The signal detector system improves upon the prior art designs by implementing modifications including: (1) the use of two peaking amplifiers for both (differential) input signals and reference to track and cancel gain variation; and, (2) the reduction of current mirroring stages to cut down current mapping error.

Abstract: Lithographic imaging of 50 nm (or less) half-pitch features in chemically amplified resists (commonly used in the manufacture of integrated circuits) is enabled by the use of reduced temperature post-exposure processing and low activation energy chemically amplified resists. The post-exposure processing preferably involves ambient to moderately elevated temperature and the presence of a deprotection reaction-dependent co-reactant (e.g., water).

Abstract: Disclosed are methods and systems for estimating a reticle bias state for a process system, that include computing a difference between control data provided to the process system and error data based on a process system output(s), and estimating the reticle bias state based on weighted measures associated with the control data, the weighted measures being based on the number of data points included in the difference. The methods and systems include associating the reticle bias state estimate with a first quality factor, computing at least one weighted measure based on a number of data elements associated with the reticle, using the weighted measure(s) to provide a computed reticle bias state estimate and an associated computed quality factor, and, comparing the computed quality factor with the first quality factor to determine whether to update the reticle bias state estimate with the computed reticle bias state estimate.

Abstract: Acid-catalyzed positive resist compositions which are imageable with 193 nm radiation and/or possibly other radiation and are developable to form resist structures of improved development characteristics and improved etch resistance are enabled by the use of resist compositions containing imaging polymer component comprising an acid-sensitive polymer having a monomeric unit with a pendant group containing a remote acid labile moiety.

Abstract: A novel semiconductor structure and method for forming the same. The semiconductor structure includes (a) a gate layer, (b) a gate dielectric layer on the gate layer, (c) a semiconductor layer on the gate dielectric layer. The semiconductor layer is electrically insulated from the gate layer by the gate dielectric layer. The semiconductor layer includes (i) first and second channel regions in direct physical contact with the gate dielectric layer and (ii) first, second, and third source/drain regions. The first channel region is disposed between and in direct physical contact with the first and second source/drain regions. The second channel region is disposed between and in direct physical contact with the second and third source/drain regions. The first, second, and third source/drain regions are directly on the gate layer.

Abstract: A method of repairing a semiconductor chip containing copper is taught, whereby copper is selectively removed from the chip. The method involves processing the chip inside a chamber in which the chip is exposed to various gases and an energy source, such as a focused ion beam. To the extent the chip may have non-copper materials, such as nitride and oxide layers, on top of the copper that is to be removed, those non-copper materials will first be selectively removed. Such removal typically results in a hole (a so-called “elevator shaft”) leading to the copper that is to be removed. Next, the method teaches the introduction of a combination of nitrogen and oxygen into the chamber and the directing of the ion beam at the spot where the copper is to be removed. In this manner, the copper on the chip is cleanly and reliably removed, without causing damage to the processing chamber.

Abstract: Compositions suitable for forming planarizing underlayers for multilayer lithographic processes are characterized by the presence of (A) a polymer containing: (i) cyclic ether moieties, (ii) saturated polycyclic moieties, and (iii) aromatic moieties for compositions not requiring a separate crosslinker, or (B) a polymer containing: (i) saturated polycyclic moieties, and (ii) aromatic moieties for compositions requiring a separate crosslinker. The compositions provide outstanding optical, mechanical and etch selectivity properties. The compositions are especially useful in lithographic processes using radiation less than 200 nm in wavelength to configure underlying material layers.

Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g.

Abstract: A method for fabricating a deep trench etched into a semiconductor substrate is provided by the present invention. The trench is divided into an upper portion and a lower portion and the method allows for the lower portion to be processed differently from the upper portion. After the trench is etched into the semiconductor substrate, a nitride layer is formed over a sidewall of the trench. A layer of oxide is then formed over the nitride layer. A filler material is then deposited and recessed to cover the oxide layer in the lower portion of the trench, followed by the removal of the oxide layer from the upper portion of the trench above the filler material. Once the oxide layer is removed from the upper portion of the trench, the filler material can also be removed, while allowing the oxide layer and the nitride layer to remain in the lower portion of the trench. Silicon is selectively deposited on the exposed nitride layer in the upper portion of the trench.

Abstract: Acid-catalyzed positive resist compositions which are imageable with 193 nm radiation and/or possibly other radiation and are developable to form resist structures of improved development characteristics and improved etch resistance are enabled by the use of resist compositions containing imaging polymer having a 2-cyano acrylic monomer.

Abstract: An interconnect structure in which a patterned anti-fuse material is formed therein comprising: a substrate having a first level of electrically conductive features; a patterned anti-fuse material formed on said substrate, wherein said patterned anti-fuse material includes an opening to at least one of said first level of electrically conductive features; a patterned interlevel dielectric material formed on said patterned anti-fuse material, wherein said patterned interlevel dielectric includes vias, as least one of said vias includes a via space; and a second level of electrically conductive features formed in said vias and via spaces.

Abstract: Form an opening in a dielectric layer formed on a substrate comprises depositing a hard mask composed of an etch resistant material over a dielectric layer, e.g. a silicon oxide. Use a photoresist mask to expose the hard mask. Use a fluorocarbon plasma to etch through the window to form an opening through the hard mask. Then etch through the hard mask opening to pattern the dielectric layer. The hard mask comprises an RCH/RCHX material with the structural formula R:C:H or R:C:H:X, where R is selected from Si, Ge, B, Sn, Fe, Ti and X is selected from O, N, S and F. The plasma etching process employs a) a gas mixture comprising N2; fluorocarbon (CHF3, C4F8, C4F6, CF4, CH2F2, CH3F); an oxidizer (O2, CO2), and a noble diluent (Ar, He); b) a high DC bias (500-3000 Volts bias on the wafer); 3) medium pressure (20-100 mT.; and d) moderate temperatures (?20 to 60°).

Abstract: A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.

Abstract: Improved endpoint detection is obtained for wet etch and/or other chemical processes involving in situ measurement of bath impedance. The endpoint detection uses a measurement apparatus having a measurement circuit with a capacitor designed to alter the phase angle of the circuit. The capacitor is preferably a variable capacitor which is used to set the initial phase angle of the measurement circuit to about zero. The methods using the improved detection enable etch to be more precisely controlled even under conditions where noise would otherwise adversely impact determination of the endpoint.

Abstract: An improved TOL process with a partial lithography-assisted sacrifcial oxide strip to prevent arsenic out-diffusion from polysilicon studs during gate oxidation. The invention prevents arsenic out-diffusion during gate oxidation from polysilicon studs by completely covering polysilicon studs with an oxide layer during gate oxidation, therby mantaining nitrogen amounts in the thin gate oxide regions, and hence, maintaining gate oxide thickness and avoiding any increase in Vt's for thin gate devices.

Abstract: A system for estimating the bandwidth of a baseband filter that produces a phase shift on arriving analog signals is disclosed. The system comprises means for generating a digital reference clock signal and means for converting the digital reference clock signal into an analog reference clock signal to be input to the baseband filter. Phase comparison means are coupled to the baseband filter for comparing the digital reference clock signal to the analog reference clock signal phase shifted through the baseband filter. A digital pulsed signal that is representative of the phase shift is generated, and digital circuit means connected to the phase comparison means convert the digital pulsed signal into a digital value, the digital value being proportional to the phase shift of the baseband filter.

Abstract: A negative resist composition, comprising: (a) silicon-containing polymer with pendant fused moieties selected from the group consisting of fused aliphatic moieties, homocyclic fused aromatic moieties, and heterocyclic fused aromatic and sites for reaction with a crosslinking agent, (b) an acid-sensitive crosslinking agent, and (c) a radiation-sensitive acid generator is provided. The resist composition is used to form a patterned material layer in a substrate.

Abstract: A solution is presented to keep track of the URLs that have been visited within an HTML file, identify the location or exit point of the last line that was displayed on a screen in a multi-screen HTML file, and return to the exact exit point location upon reentry to the web page by computing which section of the HTML file to display on the screen, and then displaying this section. The identification of whether a web page has changed after it has been visited by a user is also presented. A cyclic redundancy check is performed, comparing the current cyclic redundancy number with the last cyclic redundancy number obtained when the screen of exited multi-screen HTML file was last visited. If the web page has changed, the user has the option of viewing the web page at the top screen or going to the screen that contains the last exit position of the HTML file that was previously viewed.

Abstract: Compositions suitable for forming planarizing underlayers for multilayer lithographic processes are characterized by the presence of (A) a polymer containing: (i) cyclic ether moieties, (ii) saturated polycyclic moieties, and (iii) aromatic moieties for compositions not requiring a separate crosslinker, or (B) a polymer containing: (i) saturated polycyclic moieties, and (ii) aromatic moieties for compositions requiring a separate crosslinker. The compositions provide outstanding optical, mechanical and etch selectivity properties. The compositions are especially useful in lithographic processes using radiation less than 200 nm in wavelength to configure underlying material layers.