Patents Represented by Attorney, Agent or Law Firm Steven A. Capella
  • Method to overcome image shortening by use of sub-resolution reticle features
    Patent number: 6451490
    Abstract: Image shortening in a photolithographic process is substantially reduced by using sub-resolution reticle features to alter the aerial image in the shortened regions. The use of such sub-resolution reticle features is simple to implement in a design system, and allows for increased feature aspect ratio as well as overlap to other critical features.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: September 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: William H. Advocate, Scott J. Bukofsky, Christopher Adam Feild, Donald J. Samuels
  • Method of forming low-leakage on-chip capacitor
    Patent number: 6451662
    Abstract: An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: September 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Michael Chudzik, Oleg Gluschenkov, Raj Jammy, Uwe Schroeder, Helmut Tews
  • Semiconductor memory device with reduced orientation-dependent oxidation in trench structures
    Patent number: 6437381
    Abstract: A process for forming an oxide layer on a sidewall of a trench in a substrate. The process comprises the steps of forming the trench in the substrate, forming a nitride interface layer over a portion of the trench sidewall, forming an amorphous layer over the nitride interface layer, and oxidizing the amorphous layer to form the oxide layer. The process may be used, for example, to form a gate oxide for a vertical transistor, or an isolation collar. The invention also comprises a semiconductor memory device comprising a substrate, a trench in the substrate having a sidewall, an isolation collar comprising an isolation collar oxide layer on the trench sidewall in an upper region of the trench, and a vertical gate oxide comprising a gate oxide layer located on the trench sidewall above the isolation collar.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: August 20, 2002
    Assignee: International Business Machines Corporation
    Inventors: Ulrike Gruening, Rajarao Jammy, Helmut H. Tews
  • Dram CAM cell with hidden refresh
    Patent number: 6430073
    Abstract: A Dynamic Content Addressable Memory (DCAM) cell topology that contains fewer that can perform a “hidden” refresh of stored data that does not delay nor interrupt the CAM search cycle, thereby providing SCAM-like performance. A non-destructive read operation, is performed such that the stored-data does not have to be written back because of a refresh-read operation. A reliable CAM search can be performed after a read operation and before or even while the refresh-data is being written back. Soft-error detection processes can be performed on each CAM entry during the pendency of the refresh cycle. The DCAM cell can be used in a digital system such as a digital computer and a Network Router.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corporation
    Inventors: Kevin A. Batson, Robert E. Busch, Garrett S. Koch
  • Dummy feature reduction using optical proximity effect correction
    Patent number: 6426269
    Abstract: A method, and a system for employing the method, for providing a modified optical proximity correction (OPC) for correcting distortions of pattern lines on a semiconductor circuit wafer. The method comprises producing a mask having one or more pattern regions, and producing the semiconductor circuit wafer from the mask. The pattern regions include one or more non-edge pattern regions located adjacent to other of the non-edge pattern regions on the mask. The pattern regions further include one or more edge pattern regions located at or near an area on the mask not having the other non-edge pattern regions. The edge pattern regions have widths calculated to minimize the variance in dimensions between one or more pattern lines on the semiconductor circuit wafer formed from them and one or more pattern lines on the semiconductor circuit wafer formed from the non-edge pattern regions.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: July 30, 2002
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.
    Inventors: Henning Haffner, Heinz Hoenigschmid, Donald J. Samuels
  • Single sided buried strap
    Patent number: 6426526
    Abstract: An easily manufactured connecting structure from a node conductor of trench capacitor device is characterized at least in part by the presence of an isolation collar located above the node conductor, at least a portion of the collar having an exterior surface which is substantially conformal with at least a portion of an adjacent wall of the trench, a buried strap region in the trench above the node conductor, the strap region being bounded laterally by the isolation collar except at an opening in the collar. The connecting structure is preferably formed by a method involving clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: July 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Ramachandra Divakaruni, Jack A. Mandelman, Gary B. Bronner, Carl J. Radens
  • Mask-making using resist having SIO bond-containing polymer
    Patent number: 6420084
    Abstract: The invention provides improved resist compositions and lithographic methods using the resist compositions of the invention. The resist compositions of the invention are acid-catalyzed resists which are characterized by the presence of an SiO-containing polymer. The invention also encompasses methods of forming patterned material layers (especially conductive, semiconductive, or magnetic material structures) using the combination of the SiO-containing resist and a halogen compound-containing pattern transfer etchant where the halogen is Cl, Br or I.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: July 16, 2002
    Assignee: International Business Machines Corporation
    Inventors: Marie Angelopoulos, Ari Aviram, C. Richard Guarnieri, Wu-Song Huang, Ranee Kwong, Robert N. Lang, Arpan P. Mahorowala, David R. Medeiros, Wayne M. Moreau
  • Antireflective silicon-containing compositions as hardmask layer
    Patent number: 6420088
    Abstract: Antireflective compositions characterized by the presence of an SiO-containing polymer having pendant chromophore moieties are useful antireflective coating/hardmask compositions in lithographic processes. These compositions provide outstanding optical, mechanical and etch selectivity properties while being applicable using spin-on application techniques. The compositions are especially useful in lithographic processes used to configure underlying material layers on a substrate, especially metal or semiconductor layers.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: July 16, 2002
    Assignee: International Business Machines Corporation
    Inventors: Marie Angelopoulos, Ari Aviram, C. Richard Guarnieri, Wu-Song Huang, Ranee Kwong, Wayne M. Moreau
  • Method for direct attachment of a chip to a cooling member
    Patent number: 6413353
    Abstract: A semiconductor chip module uses a silicone adhesive between the semiconductor chip and a cap, said adhesive having sufficient bond strength to secure said cap to said chip without additional mechanical constraint while providing a direct thermally conductive path and permitting sufficient heat flow from said chip to said cap to maintain steady state operation of said semiconductor chip. The preferred silicone adhesive comprises a primerless, two-part polysiloxane-based adhesive made by reacting polydimethyl siloxane, an organosilicon compound, a polysiloxane, and a silane, in the presence of a catalyst.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: July 2, 2002
    Assignee: International Business Machines Corporation
    Inventors: Frank Louis Pompeo, Alain A. Caron, Jeffrey Thomas Coffin, Jeffrey Allen Zitz
  • Doped structures containing diffusion barriers
    Patent number: 6399434
    Abstract: Semiconductor structures having improved dopant configurations are obtained by use of barrier layers containing silicon, nitrogen, and oxygen atoms and having a thickness of about 5 to 50 Å. A doped semiconductor structure with controlled dopant configuration can be formed by: (a) providing a first semiconductor material region, (b) forming an interface layer comprising silicon, oxygen, and nitrogen on the first region, (c) forming a second semiconductor material region on the interface layer, the second semiconductor material region being on an opposite side of the interface layer from the first semiconductor material region, (d) providing a dopant in the second region, and (e) heating the first and second regions whereby at least a portion of the dopant diffuses from the second region through the interface layer to the first region.
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: June 4, 2002
    Assignee: International Business Machines Corporation
    Inventors: Susan E. Chaloux, Johnathan E. Faltermeier, Ulrike Gruening, Rajarao Jammy, Christopher C. Parks, Paul Parries, Paul A. Ronsheim, Jean-Marc Rousseau
  • Thermal modulation system and method for locating a circuit defect
    Patent number: 6400128
    Abstract: A system and method for locating a circuit defect, such as a short or an incipient open, in an electric circuit in a workpiece, such a Printed Circuit Board (PCB) or MultiChip Module (MCM). The circuit is connected to a device for sensitively measuring any resistance change. A thermal stimulus is applied to various subsets of the surface of the workpiece, the thermal stimulus being temporally modulated, and the resistance change measurement correlated with this modulation. By applying well-designed thermal stimulus subsets, resistance measurements may be logically combined which correspond to the plural thermal stimulus subsets. Further, the search region where the defect may be located may be iteratively refined. By measuring the time delay between the thermal stimulus and corresponding resistance change, the depth of a defect below the surface of the workpiece is further determined.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: June 4, 2002
    Assignee: International Business Machines Corporation
    Inventors: Daniel Guidotti, Arnold Halperin, Michael E. Scaman, Arthur R. Zingher
  • Fill strategies in the optical kerf
    Patent number: 6396160
    Abstract: Various fill strategies in the optical kerf are provided. A semiconductor wafer is divided into chip areas by strips of optical kerf regions. The optical kerf regions contain alignment marks used in the lithography processes. Partial fill patterns are provided in the optical kerf regions so that the area factor of the kerf region is similar to that of the chip areas. This results in full planarization by chemical mechanical polishing becoming feasible. Additionally, the fill is patterned so the alignment marks may be read accurately.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: May 28, 2002
    Assignee: International Business Machines Corporation
    Inventors: Steffen Schulze, Kathryn H. Varian, Timothy Wiltshire
  • Design layout for a dense memory cell structure
    Patent number: 6396096
    Abstract: A design layout for a memory cell structure is provided that achieves maximized channel length on the active areas, while not constricting the contact area of the capacitor contacts is provided.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: May 28, 2002
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.
    Inventors: Young-Jin Park, Carl J. Radens
  • Resist compositions containing bulky anhydride additives
    Patent number: 6391521
    Abstract: Acid-catalyzed positive resist compositions which are imageable with 193 nm radiation and are developable to form resist structures of high resolution and high etch resistance are enabled by the use of a combination of (a) an imaging polymer comprising a monomer selected from the group consisting of a cyclic olefin, an acrylate and a methacrylate, (b) a radiation-sensitive acid generator, and (c) a bulky anhydride additive. The imaging polymer is preferably a cyclic olefin polymer.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: May 21, 2002
    Assignee: International Business Machines Corporation
    Inventors: Hiroshi Ito, Pushkara Rao Varanasi
  • Antifuse latch device with controlled current programming and variable trip point
    Patent number: 6384666
    Abstract: A latch device is provided having a variable resistive trip point and controlled current programming. The latch device has a trip point current control element that controls an amount of current passing from a voltage source into the latch circuit, thereby varying the resistive trip point of the latch device. The latch device also has a programming current control element that controls an amount of programming current passing through the fuse element during programming. The trip point current reference and a programming current reference are provided by reference circuits having a plurality of selectable inputs that operate to change the current references binarily. An integrated circuit is also provided in which a plurality of the fuse latch devices are connected together in parallel such that the same trip point current reference and programming current reference are supplied to each latch device.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: May 7, 2002
    Assignee: International Business Machines Corporation
    Inventors: Claude L. Bertin, John A. Fifield, Russell J. Houghton, Nicholas M. van Heel
  • Polymer-bound sensitizer
    Patent number: 6383712
    Abstract: A photoresist composition for use in lithographic processes in the fabrication of semiconductor devices such as integrated circuit structures is disclosed. The photoresist composition includes a monomeric sensitizer bounding to a base-soluble long chain polymer.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: May 7, 2002
    Assignee: International Business Machines Corporation
    Inventors: Premlatha Jagannathan, Leo L. Linehan, Wayne M. Moreau, Randolph J. Smith
  • Damascene anti-fuse with slot via
    Patent number: 6380003
    Abstract: Interconnect structures comprising a substrate having a first level of electrically conductive features formed thereon; a patterned interlevel dielectric material formed on said substrate, wherein said patterned interlevel dielectric includes via spaces, wherein at least one of said via spaces is a slot via in which an anti-fuse material is formed on a portion thereof; and a second level of electrically conductive features formed in said spaces, whereby the anti-fuse material in the slot via provides a connection between the first and second levels of electrically conductive features and a method of fabricating the same.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: April 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Christopher V. Jahnes, Chandrasekhar Narayan, Carl J. Radens
  • Notched collar isolation for suppression of vertical parasitic MOSFET and the method of preparing the same
    Patent number: 6373086
    Abstract: A deep trench capacitor having a modified sidewall geometry within the collar isolation region such that the threshold voltage of the vertical parasitic MOSFET between a buried-strap out-diffusion and a N+ capacitor plate is significantly increased as compared to a conventional arrangement. By forming a concave notch within the sidewalls of the capacitor, the electrical thickness of the gate dielectric is effectively thicker than its actual physical thickness. Thereby, a reduced amount of gate dielectric and dopant is needed for suppression of vertical parasitic MOSFET conduction.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: April 16, 2002
    Assignee: International Business Machines Corporation
    Inventors: Jack A. Mandelman, Rama Divakaruni, Byeong Y. Kim
  • Low power CAM match line circuit
    Patent number: 6373738
    Abstract: A Match-Detection Circuit and Match-Detection method, for low-power-consuming searches in a Content Addressable Memory. A HIT is output when the Match Line rises from a Low voltage level to a higher Match Detection Voltage. The Match Detection Voltage is approximately the conducting threshold voltage of an N-channel Field Effect Transistor (FET), and is normally less than One Half of the Power Supply Voltage. Circuits and methods to turn of the through-current in each MISS-ing entry by a carefully timed control signal at the end of a brief Match Detection Period, are disclosed.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: April 16, 2002
    Assignee: International Business Machines Corporation
    Inventors: Fred J. Towler, Reid A. Wistort
  • Integrated fuse latch and shift register for efficient programming and fuse readout
    Patent number: 6373771
    Abstract: An integrated circuit device that obviates laser programming of a two-state element (e.g., a wire fuse or antifuse) by programming (i.e., changing) the conductive state of the two-state element according to a binary bit of programing data serially scanned in. Thereafter, the device can verify the actual programming of the two-state element by sensing the conducting condition and then serially scanning out the conductive state value of the two-sate element as a binary logic bit). The device provides the functionality of being able to test any on-chip non-memory circuitry that depends on a memory circuit being fully functional and operational while still at the wafer tester and before having to “blow” (i.e., program) any fuses.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: April 16, 2002
    Assignee: International Business Machines Corporation
    Inventors: John A. Fifield, Wayne F. Ellis, Nicholas M. van Heel