Abstract: The invention provides slurry-less chemical-mechanical polishing processes which are effective in planarizing oxide materials, especially siliceous oxides, even where the starting oxide layer has significant topographical variation. The processes of the invention are preferably characterized by the use of a fixed abrasive polishing element and by use of an aqueous liquid medium containing a polyelectrolyte for at least a portion of the polishing process involving reduction in the amount of topographic variation (height differential) across the oxide material on the substrate. The method reduces or eliminates the transfer of topographic variations to levels below the desired planarization level. The processes enable elimination of special endpoint detection techniques. The processes are also especially suitable for polishing interlevel dielectrics.

Abstract: Disclosed is a method of removing liquid from a surface of a semiconductor wafer that comprises the steps of providing a plurality of capillary channels, each said capillary channel having a first opening and a second opening, and then placing said first openings in contact with the liquid in a manner effective in drawing away the liquid by capillary action.

Abstract: Acid-catalyzed positive photoresist compositions which are imageable with 193 nm radiation and are developable to form photoresist structures of high resolution and high etch resistance are enabled by the use of a combination of cyclic olefin polymer, photosensitive acid generator and a hydrophobic non-steroidal multi-alicyclic component containing plural acid labile linking groups. The cyclic olefin polymers preferably contain i) cyclic olefin units having polar functional moieties, ii) cyclic olefin units having acid labile moieties that inhibit solubility in aqueous alkaline solutions.

Abstract: A process for forming a multilayer film stack including a noble metal electrode and a multilayer barrier. The process includes exposing the film stack to a plasma formed of reactive species from an excitable gas mixture of argon, a chlorine bearing gas, a fluorine bearing gas and a carbon bearing gas. The method of forming the lower electrode of a capacitor includes simultaneously etching a multilayer barrier and an electrode layer.

Abstract: Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.

Abstract: The invention encompasses methods for etching and/or over-etching tungsten stack structures, especially tungsten-polysilicon stack structures. The etching methods of the invention preferably employ a Cl2/NF3 etchant, optionally including O2 and/or helium. The over-etching methods of the invention preferably use a NF3/N2/O2 etchant. The methods of the invention enable effective etching of tungsten-polysilicon stacks where topographic variation is present across the substrate and/or where other tungsten stacks of different structure are also being etched.

Abstract: The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.

Abstract: Acid-catalyzed positive resist compositions which are imageable with 193 nm radiation and/or possibly other radiation and are developable to form resist structures of improved development characteristics and improved etch resistance are enabled by the use of resist compositions containing imaging polymer having a monomer with a pendant group containing plural acid labile moieties. Preferred pendant groups containing plural acid labile moieties are characterized by the presence of a bulky end group.

Abstract: A contact pin holder designs which enable the provision of more contact points in a test head space while maintaining economical and convenient pin replaceability, precise pin alignment and appropriate electrical environment. The contact pin holder enables these benefits by an improved contact pin holder design which is generally characterized by an engagement structure at the periphery of a opening in a contact support housing which engagement structure releasable engages one or more modules containing one or more contact pins.

Abstract: Semiconductor devices generally, and in particular DRAM memory devices, having buried, single-sided conductors are provided. Additionally, methods of fabricating semiconductor devices having buried, single-sided conductors are provided.

Abstract: Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of intrinsically conductive recrystallization barrier layers. The intrinsically conductive layers are preferably used adjacent to conductive strap features in trench capacitors to act as recrystallization barriers.

Abstract: A method of removing water from the surface of a silicon wafer or other substrate subjected to wet processing which includes a step of water rinsing. In this method a silicon wafer whose surface includes liquid water is disposed in an atmosphere saturated with water vapor. The water vapor is removed from the surface of the silicon wafer by a stream of water-saturated gas. Upon removal of liquid water from the surface of the silicon wafer the water vapor in the water vapor saturated atmosphere is removed by evaporation.

Abstract: The invention encompasses memory systems and/or memory modules which allow selectable clock termination between the clock/clock buffer and components of the memory modules. The invention provides a fully forward and backward compatible memory solution. The invention provides the memory modules themselves, the FET switches designed for use on the modules, and the systems that include enable/disable pins to use these modules. This invention will permit memory modules to be developed that can operate in existing (emerging) memory subsystems, as well as meet the low power/low pin count needs of future memory subsystems with no required changes to the existing/emerging systems. For 184 Pin Registered DIMMs, the power savings will equate to greater than 200 mw/DIMM, and systems will be permitted to connect DIMM clocks in serial, similar to address/control lines, thereby increasing the address/control window as well as the system read loop-back timings.

Abstract: Antireflective compositions characterized by the presence of an SiO-containing polymer having pendant chromophore moieties are useful antireflective coating/hardmask compositions in lithographic processes. These compositions provide outstanding optical, mechanical and etch selectivity properties while being applicable using spin-on application techniques. The compositions are especially useful in lithographic processes used to configure underlying material layers on a substrate, especially metal or semiconductor layers.

Abstract: Disclosed is an improved probe housing mechanism that will allow for the quick release of a probe tip from a testing tool. The invention includes a probe housing, a double cantilevered beam for holding a probe tip, and a releasable spring mechanism for holding the beam into place. The spring mechanism can be released by squeezing the spring together or by releasing a non-removable locking screw, thereby allowing the beam to be slidably removed from the probe housing for easy replacement.

Abstract: A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R—NH)4−nSiXn, wherein R is an alkyl group, n is 1, 2, or 3, and X is selected from hydrogen or the halogens. The reactive gas composition may further comprise an oxidizer and/or a reducing agent.

Abstract: Real-time analysis of output volatiles upon UV exposure is achieved using a laboratory scale apparatus. The methods and apparatus use external or internal radiation sources, especially broad band external UV radiation. The apparatus and methods of the invention are especially useful in the analysis and screening of photoresist materials. The apparatus preferably uses FTIR or MS analysis.

Abstract: A method and structure for improving a coating on a substrate comprises a chamber further comprising a rotatable holder, which holds the substrate; a supply of coating material for coating the substrate in the chamber; a window in the wall of the chamber; and a supply of liquid for coating at least a portion of the window on the interior side of the chamber. The chamber is preferably adapted to house the window in multiple configurations. A camera (or other optical detector), which is positioned outside of the chamber, monitors the substrate through the window.

Abstract: The invention provides fixed-abrasive chemical-mechanical polishing processes which are effective in rapidly reducing thickness of oxide layers, especially siliceous oxides. The processes of the invention are preferably characterized by at least one step involving simultaneous use of a fixed-abrasive polishing element and an aqueous liquid medium containing an abrasive. Where the original oxide layer has topographic variation, the thickness reduction technique of the invention may be preceeded by topography reduction step using a fixed-abrasive and an aqueous medium containing a polyelectrolyte for at least a portion of the polishing process involving reduction in the amount of topographic variation (height differential) across the oxide layer on the substrate.

Abstract: A method for forming, and a structure for a semiconductor device having vertically-oriented transistors connected to stacked capacitor cells, wherein a contact area for the capacitors enables a compact cell. A vertically-oriented transistor is formed in a trough in a substrate above a buried bit line. The gate conductor may be formed in the trough above the buried bit line, with source and drain diffusions spaced along a sidewall of the trough. Isolation regions are formed in the semiconductor substrate to isolate the transistors. Word lines are formed above the surface of the semiconductor substrate in a direction perpendicular to the direction of the buried bit lines. A capacitor contact is formed above the surface of the semiconductor substrate at a contact area of an active region between adjacent word lines. The active region is rhomboid in shape, enabling a low capacitor contact resistance, a small bit line and word line pitch, and consequently, a compact capacitor cell.