Abstract: System and method for operational risk assessment and control. The present invention, in disclosed, example embodiments provides systems and methods to facilitate risk assessment, prioritization, mitigation and control activities. Various modules work together to accomplish risk assessment, prioritization, mitigation and stability tracking. The modules can be implemented by a computer system or systems, software and networks, or by other means, such as paper-based means. In some embodiments, operational risk management and control begins with an assessment for one or more functions of the organization involved. This assessment includes identifying failure modes, causes and effects, which are permuted to define risk items. A risk prioritization report is produced which prioritizes the risk items based at least in part on the ratings associated with the causes and effects, and a mitigation plan can be put in place.

Abstract: Method and apparatus for providing film stress measurements. The invention provides a method for calculating film stress based on an inverse finite element analysis of a displaced substrate such as a semiconductor wafer. The surface displacement of the substrate is measured, and structural compliance based on an inverse finite element model of the substrate is determined. A stress field is ultimately calculated based on the structural compliance and a stress-load. The stress measurement is output based on values in the stress field. The invention can be implemented in software running on a computer system interfaced to a measurement system such as a stress and flatness gauge.

Abstract: Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM, having at least one controllable latency time generator for delaying a decoded data enable control signal with an adjustable latency time, characterized by at least one comparison circuit, which compares the cycle time of the high-frequency clock signal with a predetermined decoding time and by a signal delay circuit which can be switched on by means of the comparison circuit in order to delay the decoded data enable control signal with a predetermined delay time, in which the signal delay circuit is switched on by the comparison circuit when the cycle time of the clock signal is in a limit time region which is located about the predetermined decoding time.

Abstract: A method and apparatus for determining the position of a mobile terminal using either an internal positioning system, such as a GPS receiver, or an external positioning system such as an external cellular positioning system. A handoff procedure is used to decide which positioning system is used to calculate the position of the mobile terminal. In one embodiment, the internal positioning system is preferred and the mobile terminal switches to the external positioning system only when the internal system is unavailable, and switches back when the internal system is functioning properly. Alternatively, the external positioning system is preferred and when it is unavailable the mobile terminal switches to the internal positioning system, but switches back to the external system when it is available. In one embodiment, the mobile terminal includes the internal positioning system, a transceiver, and a mobile terminal position controller.

Abstract: Control circuit for a data path of an S-DRAM which is clocked by a high-frequency clock signal, having a programmable mode register for storing a latency value; a latency generator for temporally delaying a data path control signal, generated by an internal sequence controller, with a switchable latency; a latency decoder, which switches the latency generator in a manner dependent on the latency value stored in the mode register, provision being made of at least one signal delay element, which can be switched in by the latency decoder and serves for the signal delay of the data path control signal with a specific delay time, the latency decoder switching in the associated signal delay element if the stored latency value is high.

Abstract: Distributed RAM in a logic array. A single, customizable, logic array fabric provides both gate array logic and RAM functionality simultaneously while substantially maximizing the amount of configurable metal for routing. The extra semiconductor area in the cells of a metal limited device is used to implement general purpose RAM. Common select lines and read/write lines for the RAM are embedded in the base cells so that the configurable metal (whether via or actual metal layer) over the RAM can be used for routing logic.

Abstract: More specifically, gallium nitride semiconductor layers may be fabricated by etching an underlying gallium nitride layer on a sapphire substrate, to define at least one post in the underlying gallium nitride layer and at least one trench in the underlying gallium nitride layer. The at least one post includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a trench floor. The gallium nitride sidewalls are laterally grown into the at least one trench, to thereby form a gallium nitride semiconductor layer. However, prior to performing the laterally growing step, the sapphire substrate and/or the underlying gallium nitride layer is treated to prevent growth of gallium nitride from the trench floor from interfering with the lateral growth of the gallium nitride sidewalls of the at least one post into the at least one trench.

Abstract: Supermolecular structures and devices made from same. Semiconductor materials and devices are manufactured and provided which use controlled, discrete distribution of and positioning of single impurity atoms or molecules within a host matrix to take advantage of single charge effects. Single-dopant pn junctions and single-dopant bipolar cells are created. Each bipolar cell can function as a bistable device or an oscillator, depending on operating temperature. The cells can be used alone or in an array to make useful devices by adding an insulating substrate and contact electrodes.

Abstract: A substrate includes non-gallium nitride posts that define trenches therebetween, wherein the non-gallium nitride posts include non-gallium nitride sidewalls and non-gallium nitride tops and the trenches include non-gallium floors. Gallium nitride is grown on the non-gallium nitride posts, including on the non-gallium nitride tops. Preferably, gallium nitride pyramids are grown on the non-gallium nitride tops and gallium nitride then is grown on the gallium nitride pyramids. The gallium nitride pyramids preferably are grown at a first temperature and the gallium nitride preferably is grown on the pyramids at a second temperature that is higher than the first temperature. The first temperature preferably is about 1000° C. or less and the second temperature preferably is about 1100° C. or more. However, other than temperature, the same processing conditions preferably are used for both growth steps.

Abstract: A gallium nitride microelectronic layer is fabricated by converting a surface of a (111) silicon layer to 3C-silicon carbide. A layer of 3C-silicon carbide is then epitaxially grown on the converted surface of the (111) silicon layer. A layer of 2H-gallium nitride then is grown on the epitaxially grown layer of 3C-silicon carbide. The layer of 2H-gallium nitride then is laterally grown to produce the gallium nitride microelectronic layer. The silicon layer is a (111) silicon substrate, the surface of which is converted to 3C-silicon carbide, or the (111) silicon layer is part of a Separation by IMplanted OXygen (SIMOX) silicon substrate which includes a layer of implanted oxygen that defines the (111) layer on the (111) silicon substrate, or the (111) silicon layer is a portion of a Silicon-On-Insulator (SOI) substrate in which a (111) silicon layer is bonded to a substrate.

Abstract: In a telecommunications device having a memory, a user input device, and a modem for connection to an external network, each controlled by a processor, a dialing apparatus is provided for connection to the external network. The dialing apparatus includes a dialer program operating in the telecommunications device for prioritizing a plurality of different dialing strings, highest to lowest, each associated with the external network for connection of the telecommunications device to the external network based on the location of the telecommunications device.

Abstract: Control system for electromechanical arrangements having open-loop instability. The system is built around a control unit that processes sensing signals and provides control signals to maintain a movable member, such as a rotor or shaft, in the desired position. The control unit according to the invention includes a specially designed compensation filter, which isolates the open-loop instability so that the shaft is treated as a pure mass. In magnetic bearings, the open-loop instability is manifested as negative stiffness. The invention isolates the negative stiffness thus providing for better positive stiffness and improved bandwidth. Various filters, summers, and other operators required to carry out the invention are preferably implemented on a programmed processing platform such as a digital signal processor (DSP) or an arrangement of multiple digital signal processors.

Abstract: A gallium nitride layer is pendeoepitaxially grown on weak posts on a substrate that are configured to crack due to a thermal expansion coefficient mismatch between the substrate and the gallium nitride layer on the weak posts. Thus, upon cooling, at least some of the weak posts crack, to thereby relieve stress in the gallium nitride semiconductor layer. Accordingly, low defect density gallium nitride semiconductor layers may be produced. Moreover, the weak posts can allow relatively easy separation of the substrate from the gallium nitride semiconductor layer to provide a freestanding gallium nitride layer. The weak posts may be formed by forming an array of posts in spaced apart staggered relation on the substrate. By staggering the posts, later fracturing may be promoted compared to long unstaggered posts. Alternatively, the posts may have a height to width ratio in excess of 0.5, so that the relatively narrow posts promote cracking upon reduction of the temperature.

Abstract: A receiver is disclosed for decoding spread-spectrum coded signals received through a multi-path propagation channel to obtain decided information symbols. The receiver includes a correlator for correlating the numerical signal samples with a despreading code over information symbol periods to obtain complex correlations for different time-alignments, each time-alignment corresponding to a different one of multiple propagation paths. The receiver hypothesizes data symbol sequences, and forms channel estimates for each of the multiple propagation paths as a function of the complex correlations and the hypothesized symbol sequences and selects the most likely of the hypothesized sequences to decode the information symbols.

Abstract: More specifically, gallium nitride semiconductor layers may be fabricated by etching an underlying gallium nitride layer on a sapphire substrate, to define at least one post in the underlying gallium nitride layer and at least one trench in the underlying gallium nitride layer. The at least one post includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a trench floor. The gallium nitride sidewalls are laterally grown into the at least one trench, to thereby form a gallium nitride semiconductor layer. However, prior to performing the laterally growing step, the sapphire substrate and/or the underlying gallium nitride layer is treated to prevent growth of gallium nitride from the trench floor from interfering with the lateral growth of the gallium nitride sidewalls of the at least one post into the at least one trench.

Abstract: A method for a Digital Wireless Office System (DWOS) to establish and update a public neighbor cell list for roaming mobile stations is disclosed. Transmissions of the base stations of public cells are scanned by DWOS scanners. Information from the Digital Control Channels and Broadcast Control Channels is used in formulating the list.

Abstract: Formal verification of a logic design through implicit enumeration of strongly connected components. The invention provides for efficient, cost-effective formal verification of logical circuits and systems using a method that is much less computationally expensive than other known methods. A digraph is recursively decomposed using reachability analysis. Non-trivial, strongly connected components derived through the use of the invention can be compared to expected behavior of a circuit or system. Alternatively, the invention can be applied to detect so-called “bad cycles” which are encountered in many formal verification problems.

Abstract: Embodiments of the present invention pendeoepitaxially grow sidewalls of posts in an underlying gallium nitride layer that itself is on a sapphire substrate, at high temperatures between about 1000° C. and about 1100° C. and preferably at about 1100° to reduce vertical growth of gallium nitride on the trench floor from interfering with the pendeoepitaxial growth of the gallium nitride sidewalls of the posts. Thus, widely available sapphire substrates may be used for pendeoepitaxial of gallium nitride, to thereby allow reduced cost and/or wider applications for gallium nitride devices. More specifically, gallium nitride semiconductor layers may be fabricated by etching an underlying gallium nitride layer on a sapphire substrate, to define at least one post in the underlying gallium nitride layer and at least one trench in the underlying gallium nitride layer. The at least one post includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a trench floor.

Abstract: Methods of forming compound semiconductor layers include the steps of forming a plurality of selective growth regions at spaced locations on a first substrate and then forming a plurality of semiconductor layers at spaced locations on the first substrate by growing a respective semiconductor layer on each of the selective growth regions. The first substrate is then divided into a plurality of second smaller substrates that contain only a respective one of the plurality of semiconductor layers. This dividing step is preferably performed by partitioning (e.g., dicing) the first substrate at the spaces between the selective growth regions. The step of forming a plurality of semiconductor layers preferably comprises growing a respective compound semiconductor layer (e.g., gallium nitride layer) on each of the selective growth regions. The growing step may comprise pendeoepitaxially growing a respective gallium nitride layer on each of the selective growth regions.

Abstract: Multiple function bandwidth management systems. Bandwidth-management systems for an optical network are easily assembled by concatenating a plurality of intelligent, miniaturized, bandwidth-management modules (BMM's) together. The BMM's subdivide the wide available spectrum into narrow band segments. Each individual BMM is designed to overcome loss and optimize dispersion, gain, and power or gain equalization for a few channels at a time. Each device includes optical connectors and filters, as well as any other components necessary to direct the band of optical channels through the device's optical path while passing other optical channels within the spectrum to additional devices which can be connected without disturbing existing bandwidth-management modules. Each BMM also includes a digital control module that operates the BMM in any one of a plurality of selectable operating modes.