Abstract: A method and apparatus are provided for controlling a performance characteristic of an electronic device. In one form, the electronic device includes a frame, a first subassembly on the frame and including a component encoded with a measured value of a first performance characteristic of the first subassembly, a download circuit on the frame to download the measured value from the encoded component, and an electronic circuit on the frame to a) receive a signal from the download circuit representative of the measured value and b) control a second performance characteristic of the electronic device as a function of the signal.

Abstract: Adjustable optical fiber grating dispersion compensators. The invention provides a fully tunable dispersion compensator with a wide dynamic range. Dispersion compensators according to the invention are based on uniform fiber Bragg grating technology. Individual gratings are tuned so that the gratings, which normally operate in reflection mode, operate in transmission mode with the frequency of interest falling just outside a reflection band edge. Gratings are combined to provide broadband, or multiple-wavelength dispersion. Tuning is provided via transducers coupled to the gratings. A control system can be connected to the transducers to provide a control signal so that the frequencies of the gratings can be dynamically tuned. The control system operates by measuring signals from opto-electronic detectors. The signals are used to determine a fractional spectral power transmitted through a filter. The fractional spectral power is related to the amount of dispersion present in the optical path of the network.

Abstract: Customer premises equipment (CPE) which allows a user programmable access carrier selection. Users can program one or more alternate access carriers to use at different times and/or different days of the week. After the feature has been programmed, the CPE determines which access carrier to use and inserts the appropriate alternate access code prior to releasing the dialed digits. The invention allows a telephone customer to take advantage of varying rates and promotional programs without having to remember the details of each provider's plans and the provider access codes for each call.

Abstract: Hard, real-time, multi-tasking system is monitored by combined hardware and software and logic to detect overrun of any task beyond a declared maximum processor cycle limit for the task. Processor execution cycles utilized by DMA or interrupt processing and not related to the task being executed are not counted. Counter hardware and control logic reduces software overhead for monitoring execution cycle utilization by a task and provides capability not only of overrun detection, but programmed cycle usage alarm, consumed cycle count and overall processor loading or utilization measurements to be made.

Abstract: A method and apparatus for obtaining near 100 percent quiescent current test coverage within a reasonable amount of time is accomplished by providing a plurality of test circuits interdisposed between a plurality of combinational logic circuits. During testing, the testing circuits isolate the input of one combinational logic circuit from the output of the preceding combinational logic, thus allowing the test circuit to stimulate the input of the combinational logic circuit. By performing the input stimulations of the plurality of combinational logic circuits simultaneously, only two test steps are needed to check the quiescent current of the plurality of combinational logic circuits.

Abstract: Method and apparatus for dynamic control of power management circuitry in a microprocessor. A clock and power management subsystem within the microprocessor contains clock generation and control logic and a powered-down mode register. The register is controlled by register control logic in the microprocessor and determines the powered-down mode of the various hardware units that make up the microprocessor. The clock generation and control logic also receives a powered-down mode enable signal from each of the hardware units. The hardware unit receive a re-power-up signal which, when activated and deactivated, can cause the hardware units to de-activate and activate, respectively, the powered-down mode enable signal.

Abstract: A magnetoresistive spin valve sensor is described. Such a sensor is also known as a GMR sensor or giant magnetoresistive sensor. The layers (24, 26, 28) of the sensor are mounted on a substrate (20) having steps or terraces on one of its face. The steps or terraces on the substrate's surface cooperate with one or more of the ferromagnetic layers (24, 28) of the sensor to determine the layers' magnetic properties. Specifically, the thickness of one or more of the sensor's layers can be set above or below a critical thickness which determines whether the easy direction of uniaxial magnetization of a layer of that particular material is fixed or "pinned". If pinned, the layer has a high coercive field. Thus, the new device avoids a biasing layer to pin any of the magnetic layers. Preferably the easy axes of the first two ferromagnetic layers (24, 28) are set at 90.degree. to one another in the zero applied field condition by appropriate choice of layer thickness.

Abstract: Bus performance in a computer system having multiple devices accessing a common shared bus may be improved by increasing throughput and decreasing latency while accounting for dynamic changes in bus usage. Devices submit a priority level along with a bus request to a bus controller. Upon receiving multiple requests, an arbiter of the bus controller compares the priority levels associated with the different bus requests and grants control of the bus to the device having the highest priority level. During each cycle that a device has control of the bus, a feedback logic circuit of the bus controller determines whether other bus requests are pending, and if so, determines the highest pending request priority level. Signals corresponding to the results of these determinations are fed back to each device.

Abstract: Large signal swings are obtained for the transmitted signal of a telephone line modem using differential drivers. Compensation for the complex nature of line impedance is provided without affecting the response of the receive circuits. Common-mode noise is effectively cancelled due to a fully balanced topology for the transmit and receive portions of the hybrid circuit.

Abstract: A time-division multiplexing synchronization mechanism employs a 1-bit/frame framing channel with a pattern that repeats every 2 frames. Acquisition and reacquisition of synchronization with such a framing pattern is enabled through the use of an explicit synchronization procedure. With this procedure, initial acquisition of frame synchronization as well as reframing after loss of synchronization are carried out while the transmission channel is carrying only a predefined bit pattern. When the receivers are in synchronization, synchronization is monitored and maintained using a 1-bit/frame framing channel, while the communications link is carrying multiplexed bit streams with the appropriate format.

Abstract: A telephone interface protection circuit and modem incorporating the telephone interface protection circuit. The circuit includes a sensing circuit and a determining circuit. The interface protection circuit checks for an active telephone line and checks the line for over-current conditions caused when a modem designed for the public switched telephone network is plugged into a private digital telephone network. The circuit functions when the modem is operating to provide continuous monitoring. It can be built as a stand-alone device or incorporated into a modem. The circuit notifies the user of the line condition either with LEDs or with a status message sent to the user via the host computer interface.

Abstract: A specific structure which improves the decoupling capacitance for the power conductors in parallel metal layers of a semiconductor device. The power conductors are arranged so that conductors vertically adjacent to each other in the two outer of three metal layers are never connected to the same supply voltage terminal, but rather to opposing terminals. To improve current carrying capacity and reduce area, a power conductor in one outer plane is connected to a power conductor in the other outer plane which is displaced vertically and laterally from the first power conductor. The connection is made through special stitch conductors in the intervening plane. The resulting structure improves power supply decoupling for the finished device by providing significantly greater capacitance associated with the power distribution system of the chip.

Abstract: Scaling of video is performed using area weighted averaging of input pixels to calculate coefficients to multiply with luminescence and crominence of input pixels. Such coefficients are produced for both the vertical and horizontal scaling directions of the input video stream. When scaling down or scaling up, scaling is first performed in the vertical direction to produce partially scaled pixels, which are then utilized for scaling in the horizontal direction. When scaling up, a pre-interpolation or pre-replication process is utilized to double the inputted pixel grid which doubled pixel grid is then utilized to scale down to the desired pixel grid size, which is greater than the originally inputted pixel grid size.

Abstract: A temperature compensated resistance current generator. The generator provides temperature compensated reference current in a digital CMOS environment where resistors with positive temperature coefficients are not available, and where temperature coefficients are large. The current generator has two current sources and a subtraction circuit which subtracts the current from one current source from the current from the other current source to create a primary current. A proportionality circuit multiplies the primary current by a constant to produce the generator output.

Abstract: A massively parallel processor apparatus having an instruction set architecture for each of the N.sup.2 the PEs of the structure. The apparatus which we prefer will have a PE structure consisting of PEs that contain instruction and data storage units, receive instructions and data, and execute instructions. The N.sup.2 structure should contain "N" communicating ALU trees, "N" programmable root tree processor units, and an arrangement for communicating both instructions, data, and the root tree processor outputs back to the input processing elements by means of the communicating ALU trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 PEs, identified as PE.sub.column,row, in a N root tree processor system, placed in the form of a N by N processor array that has been folded along the diagonal and made up of diagonal cells and general cells. The Diagonal-Cells are comprised of a single processing element identified as PE.sub.

Abstract: An audio system is provided for generating audio sound for a host computer. It includes an interface connector for connection with the host computer; an interface controller for communicating with the host computer using the interface connector; a trap adapted to trap audio instruction signals from an application running on the host, such as a game having an audio portion; a trap controller adapted to control the trap; and an audio output. The system operates with an interface communicator which is adapted to respond to a request from the interface controller to read information from the trap and send audio output instruction to the audio output to generate audio sound.

Abstract: Video data is decompressed in a coder/decoder (CODEC) and then scaled in a scaler device before being provided to a frame buffer within a display adapter of a data processing system. Since the scaling of the video data often results in a significant increase in the required bandwidth, a buffer implemented within the scaling device may reach a threshold level whereby it is not desired that any more scaled data be received before being transmitted to the frame buffer. When such a threshold level is reached, a stall signal is sent to the interface between the scaler device and the CODEC device providing the pixel data, which results in the stopping of the transmission of pixel data from the CODEC to the scaler device. Assertion of the stall signal results in the suspension of the transmission of the horizontal and vertical synchronization signals and the pixel clock signal from the scaler device to the CODEC device.

Abstract: A bi-directional current source which maintains accurate, substantially equal source and sink currents over a large range of output voltages. The current source includes a primary field effect transistor (FET) and two mirroring FET's. It additionally includes at least one operational amplifier for voltage balancing. An optional operational amplifier provides and additional bias voltage and transistor matching optionally provides impedance matching of the supply voltages.

Abstract: A system and method of partitioning and providing communication to allow ISA Plug and Play protocol logic functions to be shared across multiple integrated circuits on a single Plug and Play compliant ISA bus adapter card as defined by the Plug and Play ISA Specification in a manner that minimizes the duplication of function.

Abstract: A hot-plugging circuit associated with a backplane or motherboard for controlling the rate of application of voltage and current to a non-operating printed-circuit card in the process of being inserted into a backplane connector in a system including other already-operating printed-circuit cards. Each backplane connector has connector contacts of two different lengths. An isolation diode at each connector is connected to two of the longer contacts of the connector and is forward biased by a non-operating printed-circuit card being inserted into that connector. The forward-biased isolation diode triggers a card insertion circuit to recognize that a non-operating printed-circuit card is in the process of being inserted. The card insertion circuit triggers a voltage and current control circuit to ramp up the voltage and current furnished to the non-operating printed circuit.