Abstract: Image processing for multimedia workstations is a computationally intensive task requiring special purpose hardware to meet the high speed requirements associated with the task. One type of specialized hardware that meets the computation high speed requirements is the mesh connected computer. Such a computer becomes a massively parallel machine when an array of computers interconnected by a network are replicated in a machine. The nearest neighbor mesh computer consists of an N.times.N square array of Processor Elements(PEs) where each PE is connected to the North, South, East and West PEs only. Assuming a single wire interface between PEs, there are a total of 2N.sup.2 wires in the mesh structure.

Abstract: An ATM communications network includes a system processor having a device driver and a memory coupled to an adapter at an interface. Frames stored in the memory are transmitted to the network using a transmit ready queue residing in the adapter and defined by transmit control registers. The frames are linked together by descriptors and pointers to received ready lists maintained by the device driver. A transmit frame complete list is established in the system memory using the transmit control registers. An interrupt is generated by the adapter indicating when frame transmission is complete. Simultaneously, cells are received from the network and stored in system memory according to a free buffer list established by the device driver. A pointer is maintained by the device driver to the last entry of the receive free buffer list. The adapter maintains a pointer to the next buffer to be used from the receive free buffer list.

Abstract: Method and system for providing user-controlled, continuous, synchronized variable-speed playback of a previously recorded digital audio/video presentation. The user directly controls the rate of playback and the audio and video remain synchronized. The audio is expanded or compressed using the time domain harmonic scaling method so that the pitch of the audio remains undistorted. Synchronization is maintained by allowing one clock to serve as the master time clock for the system. The clocks which can serve as the master time clock include the audio decoder clock, the video decoder clock, and the system clock. The invention is particularly useful in multimedia display systems designed to display MPEG data.

Abstract: A video register interface for a video processor in which each frame register has a first storage element which is written by a microprocessor interface independently from a second storage element which outputs control data to video processing circuitry. Since reading and writing are done independently to different storage elements, the contents of the register can be changed without adverse effects on a displayed image. The register interface is used in a CMOS video processor which in turn is used in a microprocessor based multimedia computing system.

Abstract: Image processing for multimedia workstations is a computationally intensive task requiring special purpose hardware to meet the high speed requirements associated with the task. One type of specialized hardware that meets the computation high speed requirements is the mesh connected computer. Such a computer becomes a massively parallel machine when an array of computers interconnected by a network are replicated in a machine. The nearest neighbor mesh computer consists of an N.times.N square array of Processor Elements(PEs) where each PE is connected to the North, South, East and West PEs only. Assuming a single wire interface between PEs, there are a total of 2N.sup.2 wires in the mesh structure.

Abstract: A circuit embodied within an adapter card for hot-plugging with a card slot in a card slot coupled to a processor based system utilizes a biasing circuit for ensuring that the input voltage to the load of the adapter card is of a sufficient magnitude. The circuit also includes a FET/feedback circuit for opening and closing the circuit provided between the input voltage to the adapter card and the load. This FET/feedback circuit operates as a constant current source to charge the input capacitance of the load and converts to a switched mode when the load capacitance is fully charged. The biasing circuit controls the FET/feedback circuit so that it remains open during hot-plugging of the adapter card into the card slot to alleviate pin arching. A monitor/timer circuit prevents the FET/feedback circuit from operating in the constant-current mode for no longer than a predetermined amount of time.

Abstract: A local area network (LAN) interface port with a simple overcurrent protection circuit which isolates the power supply connection for the port from fault conditions on the LAN. The circuit has a normally-on field effect pass transistor in line with the load terminal. The pass transistor shuts off when a fault condition is detected. Such a condition is detected when the voltage across a sense resistor becomes greater than the voltage across a reference resistor. A current mirror is made up of a transistor array and the sense and reference resistors. The current mirror compares the two voltages, and a bipolar transistor switches the gate voltage of the pass transistor on when the fault condition is detected. The design is particularly useful with the LAN system specified in ANSI/IEEE Standard 802.3, commonly known as Ethernet.

Abstract: A folded memory array structure that can be used with a folded processor array structure to make cosine transform calculations faster and more efficient. The memory elements of the folded memory array are interconnected is if an M by M element square array of single memory elements were logically folded or cut and overlain to form an N by N node subarray where each node has multiple interconnected memory elements. The subarray is than logically folded and the nodes connected by buses and switches as if the resultant array were folded along the diagonal, producing a triangular memory array structure. This transposed folded memory array is enhanced with computational elements disposed at the nodes of the array. A computational array processor is thereby formed which can perform cosine transform operations efficiently for multimedia, video, and other applications.

Abstract: A small and efficient control circuit for a compensated CMOS off-chip driver and a driver circuit incorporating the control circuit. The control circuit uses an exclusive OR gate as a phase detector to determine the phase difference between a system clock and a delayed version of the system clock. An RC filter smooths the output of the exclusive OR gate to produce a voltage proportional to the delay introduced in the CMOS circuitry by environmental and process variables. The voltage from the RC filter is used as a control voltage to control the effective channel width of the effective pull-down device of the off-chip driver circuit. An off-chip driver using the control circuit is used in the I/O unit of a CMOS integrated circuit chip.

Abstract: A single-port network node transceiver that does not draw any substantial current from the network when it is powered-down, enabling it to meet the ISDN powered-down loading specification when built on a CMOS integrated circuit chip. The pull-up transistors of the transmitter output circuit each have means for shorting the well terminal to source terminal connection when the circuit is operating and opening the connection when the power to the transceiver is shut down. The opening of this connection prevents the well-substrate junction of the pull-up transistors from becoming forward biased and drawing current from the network when the power to the transceiver is off and there is voltage present on the network. The transceiver also includes a plurality of ESD overvoltage protection diodes in series between the power supply rail and each input/output terminal.

Abstract: Method and apparatus for managing internal-node communications in a packet switching network by calculating optimal routes for packets and addressing subnodes within packet nodes using a specific message format. Internal communication facilities called intranode links connect multiple subnodes within nodes. Each subnode contains a switching mechanism and routes packet to other nodes, subnodes, or user applications using a specific message format. The message format allows specific subnodes anywhere in the network to the addressed by any other subnode, making communications more efficient and simplifying the management of internode links.

Abstract: A VLSI chip is disclosed having reduced power dissipation. This is accomplished by limiting the output voltage swing at the output of off chip driver circuits by utilization of a control circuit to regulate the gate bias voltage of an NFET pull-up transistor coupled to the output of the driver circuit and by feeding back the output of the driver circuit to the control circuit.

Abstract: Visual inspection device for inspecting the finish on manufactured goods. A plurality of samples are joined together in a substantially flat, substantially disk-like shape for easy viewing. The device includes a viewing hole in the center so that the surface being inspected can be viewed both through the hole and on the outside of the device, thus making comparisons by eye more accurate. The device optionally includes radial slots so that multiple devices can be fastened together or a device can be fastened to another object.

Abstract: Method and apparatus for tagging a service request and the responses to a service request in a pipeline program running on a task in a multitasking computer system. Each service request made to a service supplier from a pipeline stage is tagged with a unique identifier string that is automatically returned to the pipeline with the response to the service request. A time manager stage monitors the unique identifiers appended to responses directed into the pipeline and uses the identifiers to correlate each response to a specific, previously sent request. The time manager then directs the responses to the appropriate destination stage. The time manager also discards responses that are no longer needed either because the appropriate destination stage or pipeline is no longer active, or because a user specified time-out interval has elapsed.

Abstract: A tristate buffer circuit for mixed voltage applications. The circuit is built from field effect transistors and is used as an output buffer in applications where a low voltage component needs to drive both components which are powered by the same low voltage and components which are powered by a higher voltage. The circuit uses a floating n-well technique in combination with a pass-gate network, a one-shot circuit, and a process-dependent bias voltage reference. It is particularly useful on CMOS semiconductor chips which have bus interfaces, such as local area network (LAN) protocol chips.

Abstract: Method and apparatus for making limited internal-node communication facilities externally visible in a packet switching network. Internal-node communication facilities are called intranode links, can include any cable, channel, bus, etc. over which data passes, and are used to connect the multiple subnodes within a given node. Each subnode contains a switching mechanism and routes packets to other nodes, subnodes, or user applications. Each node provides network control functions such as topology, directory, path selection, and bandwidth management which can manage intranode links in the same manner that internode links are currently managed.

Abstract: A phase lock loop circuit (PLL) is manufactured as a part of each very large scale integrated circuit (VLSI) that might need clock pulses. When these VLSI chips are mounted on a printed circuit board (PC), three crystal oscillators are also mounted on the PC in order to provide redundancy. In order to identify crystal oscillators that are less desirable from the standpoint of operation and accuracy, a circuit is mounted on the PC for comparing oscillator frequencies and detecting when lack of frequency agreement is noted. A gating circuit receives the output of the detecting circuit for selecting and passing clock pulses only from a properly functioning crystal oscillator to the rest of the PC. Programmable counters are provided in the PLLs to allow local generation within each VLSI of clock pulses at a frequency that is a ratio of the frequency of the crystal-generated clock pulses that are circulated throughout the PC.

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc.

Abstract: A content addressable memory in accordance with the present invention includes a number of bistable memory cells having as inputs thereto first and second bit lines and an address line, and a COMPARE circuit connected to each of the memory cells so as to provide the COMPARE function without loading the first and second bit lines and including means for inhibiting current flow when a miscompare occurs.

Abstract: An adapter cable and card for interfacing a personal computer to a local area network or other type of computer network which can operate on either of two types of media. The cable uses a symmetrical plug connector which mates with a receptacle connector on the adapter card in either a first position, or a second position which is 180 degrees rotated from the first position. In the first position, signal lines for one type of media are connected and signal lines for the other type of media are disconnected. In the second position, signal lines for the second type of media are connected, and signal lines for the first type are disconnected. The disconnection of the unused conductors allows the drive circuits for unused type of media to remain active without causing electromagnetic interference problems.