Patents Represented by Attorney, Agent or Law Firm Steven F. Caserza
  • Patent number: 4441082
    Abstract: An AGC circuit (12) contains a programmable gain stage comprising an operational amplifier (150) and one or more capacitor arrays (101, 121) for controlling the closed loop gain of the operational amplifier. The output signal (V.sub.O) of this operational amplifier is rectified, and the rectified signal is alternately integrated with a reference voltage (V.sub.ref) of opposite polarity to the rectified AGC signal. The polarity of the integrated voltages operates a counter stage (200). The output bits (0.sub.2 -0.sub.N) of the counter are used to control switches (134-2 through 134-N, 135-2 through 135-N, 110-2 through 110-N, 111-2 through 111-N) in the one or more capacitor arrays which control the closed loop gain of the operational amplifier of the AGC circuit of this invention.
    Type: Grant
    Filed: October 9, 1981
    Date of Patent: April 3, 1984
    Assignee: American Microsystems, Inc.
    Inventor: Yusuf A. Haque
  • Patent number: 4438354
    Abstract: A switched capacitor gain stage (110, 120) having a programmable gain factor. This gain factor is determined by the connection of desired gain determining components (14-17; 25-28) contained within a component array (100, 101). A sample and hold circuit (46) is provided for the storage of the error voltage of the entire gain-integrator stage. This stored error voltage (V.sub.error) is inverted and integrated one time for each integration of the input voltage (V.sub.in), thus eliminating the effects of the inherent offset voltages of the circuit from the output voltage (V.sub.out).
    Type: Grant
    Filed: August 14, 1981
    Date of Patent: March 20, 1984
    Assignee: American Microsystems, Incorporated
    Inventors: Yusuf A. Haque, Vikram Saletore, Jeffrey A. Schuler
  • Patent number: 4434222
    Abstract: A photoconductor material having high sensitivity to infrared light is provided therefore making it suitable for use in laser printers. The photoconductor of this invention has a dark decay of approximately 40 volts/second, thereby enhancing the use of this invention with infrared laser printers as compared to prior art infrared sensitive photoconductors. The photoconductor of this invention comprises cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium carbonate (CdCO.sub.3) and cadmium oxide (CdO) in a binder, and preferably also includes a small amount of copper dopant. The photoconductor of this invention is prepared by adding ammonia to a suspension of cadmium sulfide/cadmium carbonate in water and then adding hydrogen selenide to this suspended solution.
    Type: Grant
    Filed: May 15, 1981
    Date of Patent: February 28, 1984
    Assignee: Benson, Inc.
    Inventors: Mary J. Wegener, Morris Feinleib
  • Patent number: 4432070
    Abstract: A semiconductor memory device (100) utilizing a programming transistor (54) capable of switching high programming currents, and a read transistor (53) capable of sensing the state of the cell (i.e. programmed or unprogrammed). The programming transistor, utilized only when programming the cell, being rather large, is rather slow. The read transistor, utilized only when reading the cell, is constructed to be as small as possible, thereby achieving a substantially increased reading speed over prior art PROM devices which utilize a single transistor per memory cell for both programming and reading.
    Type: Grant
    Filed: September 30, 1981
    Date of Patent: February 14, 1984
    Assignee: Monolithic Memories, Incorporated
    Inventor: William E. Moss
  • Patent number: 4431986
    Abstract: A digital to analog converter (100) utilizes a current mirror connected to a reference voltage (V.sub.REF) to generate a constant reference current (I.sub.REF). A voltage divider (R.sub.1 and R.sub.2) is used in conjunction with a plurality of MOS transistors (X.sub.1 -X.sub.N) serving as current mirrors having specific current carrying capabilities which are controlled by selected binary digits (bits) of a digital signal. By the appropriate connection of desired ones of said plurality of MOS transistors, a specific fraction of said reference current is caused to flow through said plurality of MOS transistors. The amount of current flowing through said plurality of MOS transistors generates an output voltage (V.sub.OUT) from the digital to analog converter of this invention. This output voltage may be positive or negative with respect to the reference voltage, thus the output voltage is bipolar.
    Type: Grant
    Filed: October 9, 1981
    Date of Patent: February 14, 1984
    Assignee: American Microsystems, Incorporated
    Inventors: Yusuf A. Haque, Vikram Saletore, Jeffrey A. Schuler
  • Patent number: 4431971
    Abstract: A unique dynamic operational amplifier is constructed utilizing a switched capacitor (25) as the biasing means, wherein the switched capacitor biasing means is capable of effectively doubling the power supply voltage supplied to the dynamic operational amplifier, thus greatly extending the range of the input voltage (V.sub.IN) and output voltage (V.sub.OUT) of the dynamic operational amplifier.
    Type: Grant
    Filed: August 17, 1981
    Date of Patent: February 14, 1984
    Assignee: American Microsystems, Incorporated
    Inventor: Yusuf A. Haque
  • Patent number: 4422155
    Abstract: This invention provides a uniquely designed switched capacitor multiplier/adder (129) which also functions as a digital-to-analog converter in a single subcircuit. The multiplier/adder, in a single operation, multiplies an analog voltage by a binary coefficient, and sums this product with a second analog voltage. The use of this unique subcircuit results in a significant reduction in space requirements for the construction of, for example, a speech synthesis circuit utilizing linear predictive coding over prior art circuits. This reduction in size results in a significant reduction in the manufacturing costs for this circuit over prior art circuits, and additionally allows the option of including on the speech synthesis chip a memory for the storage of binary representations of to-be-synthesized speech patterns.
    Type: Grant
    Filed: April 1, 1981
    Date of Patent: December 20, 1983
    Assignee: American Microsystems, Inc.
    Inventors: Gideon Amir, Roubik Gregorian, Ghanshyam Dujari
  • Patent number: 4419539
    Abstract: A structure for transmitting an optical signal which allows physical separation of the optical source from the point of optical output, thereby preventing noise or interference due to the optical source being located in the vicinity of sensitive electrical apparatus.
    Type: Grant
    Filed: October 24, 1980
    Date of Patent: December 6, 1983
    Assignee: Arrigoni Computer Graphics
    Inventor: David M. Arrigoni
  • Patent number: 4419679
    Abstract: A recording head for use in an electrostatic printer comprises four staggered rows of styli. Signals for driving each row of styli are transmitted through a buffer wherein the signals for the first row of styli are transmitted without delay to the styli, the signals for the second row of styli are transmitted with an appropriate delay of a first selected time, the signals for the third row of styli are transmitted with an appropriate delay of a second selected time and the signals for the fourth row of styli are transmitted with an appropriate delay of a third selected time. The delay means comprises a random access memory driven by address counters controlled by a control sequencer to function as a delay. The four staggered rows of styli are formed by a novel method wherein the styli in the second row are formed between the styli in the first row and the stylis in the third and fourth rows are formed by making use of the grooves formed between the styli in the first and second rows.
    Type: Grant
    Filed: June 3, 1980
    Date of Patent: December 6, 1983
    Assignee: Benson, Inc.
    Inventors: Sherman L. Rutherford, Arthur E. Bliss, Noel J. Schmidt
  • Patent number: 4417391
    Abstract: A recording head for use in an electrostatic printer comprises four staggered rows of styli formed by a novel method wherein the styli in the second row are formed between the styli in the first row and the styli in the third and fourth rows are formed by making use of the grooves formed between the styli in the first and second rows. By forming the rows of styli on a cylindrical drum, two recording heads are obtained from each fabrication run wherein the recording head in one set of styli is the mirror image of the recording head in the other set of styli. Should an error occur in the manufacture of the styli by placing the third row of styli in the grooves where the fourth row of styli normally belongs, the resulting recording heads are identical to those obtained with the proper placement of the third and fourth rows with the exception that the position on the drum of each type of recording head is reversed.
    Type: Grant
    Filed: June 8, 1982
    Date of Patent: November 29, 1983
    Assignee: Benson, Inc.
    Inventors: Sherman L. Rutherford, Arthur E. Bliss, Noel J. Schmidt
  • Patent number: 4417325
    Abstract: A memory cell comprises a substrate of a first conductivity type (preferably N type) in which is formed a first region of opposite conductivity type. Second, third and fourth regions of first conductivity type are then formed in the first region, said second and third regions being separated by a first portion of the first region and said third and fourth regions being separated by a second portion of the first region. A fifth region of first conductivity type is then formed in the second portion of the first region and a first electrode is attached to the fifth region. This electrode is electrically isolated from the second, third and fourth regions and extends on insulation over the first portion of said first region to said second region and also extends over said third region and a part of the second portion of said first region. This electrode is covered by insulation.
    Type: Grant
    Filed: July 13, 1981
    Date of Patent: November 22, 1983
    Inventor: Eliyahou Harari
  • Patent number: 4415941
    Abstract: A linear actuator for translating accessing transducers such as read/write heads along a straight line path of travel relative to a rotating magnetic disk includes a carriage, a flat coil mounted to the disk and having an effective winding extending transversely at the rear end of the carriage, one pair of rollers mounted at right angles to each other at one side of the carriage in rolling engagement upon a cylindrical guide rail, two pairs of rollers similarly mounted at the other side of the carriage in rolling engagement upon a second guide rail. The second guide rail is fixedly mounted to a base frame; the other guide rail is pivotally mounted parallel to the other rail and is biased by a spring to preload the single pair of rollers against the pivotal rail. A pair of block magnets are mounted at the rear end of the base frame with a gap therebetween that is aligned with the path of travel of the effective winding.
    Type: Grant
    Filed: June 29, 1981
    Date of Patent: November 15, 1983
    Assignee: Atasi Corporation
    Inventors: Frank C. Gibeau, Paul L. Farmer
  • Patent number: 4414594
    Abstract: A dual motor linear actuator is disclosed for use in a magnetic disc drive device. It includes a carriage reciprocatably guided between a pair of guide rails, with the accessing transducers being mounted to its inner end. Separate rectangular drive coils are affixed in symmetrical outboard relationship at the sides of the body of the carriage. The actuator assembly further includes two pairs of slab shaped magnets mounted to E-shaped magnet support structures that are integrally formed with the base of the disc drive device. The magnets are mounted to form two air gaps that are symmetrically disposed relative to a center plane and so that they respectively cooperate with the drive coils to apply motive forces on the carriage generally along two lines that are equidistantly spaced from the aforesaid plane of symmetry. The outer ends of pole pieces of the two magnet support structures are rigidly interconnected by a single plate that acts as an end pole piece for both magnet support structures.
    Type: Grant
    Filed: February 26, 1982
    Date of Patent: November 8, 1983
    Assignee: Atasi Corporation
    Inventors: Paul L. Farmer, Frank C. Gibeau, Stanley F. Brown, Garold W. Plonczak
  • Patent number: 4409726
    Abstract: This invention significantly reduces the problem of undesired lateral diffusion of P type dopants into the P type active area. A thin oxide/nitride sandwich is formed on the surface of a semiconductor wafer and patterned to serve as a mask defining the to-be-formed active areas. An N type dopant implant is performed on the surface of the wafer to establish the desired field inversion threshold voltage. The wafer is then oxidized, with the oxide/nitride sandwich preventing oxide growth in the active areas. A layer of photoresist is applied to the wafer and patterned to expose the to-be-formed P well. That portion of the oxide exposed by the photoresist is removed, as is that portion of the substrate within the to-be-formed P well which contains N type dopants. P type impurities are then applied to the wafer. The photoresist is then removed and the P type dopants are diffused with little oxide growth to provide a P well having the desired dopant profile.
    Type: Grant
    Filed: April 8, 1982
    Date of Patent: October 18, 1983
    Inventor: Philip Shiota
  • Patent number: 4410964
    Abstract: A memory device is constructed having a plurality of output ports, each output port being one word wide, such that a plurality of words may be accessed from the memory simultaneously.
    Type: Grant
    Filed: December 8, 1980
    Date of Patent: October 18, 1983
    Inventors: Karl I. Nordling, Scott Nance
  • Patent number: 4410904
    Abstract: A semiconductor READ ONLY MEMORY (ROM) device is constructed by using a series of word lines as a mask during the fabrication of the underlying bit lines. The width of the word lines over each memory cell determines the characteristics of that cell (i.e. programmed or unprogrammed).
    Type: Grant
    Filed: October 20, 1980
    Date of Patent: October 18, 1983
    Assignee: American Microsystems, Inc.
    Inventor: Donald L. Wollesen
  • Patent number: 4409723
    Abstract: The floating gate in an N channel EPROM cell extends over the drain diffusion and over a portion of the channel thereby to form a "drain" capacitance between the drain and the floating gate and a "channel" capacitance between the channel and the floating gate. A control gate overlaps the floating gate and extends over the remainder of the channel near the source diffusion thereby to form a "control" capacitance between the channel and the control gate. These three capacitances form the coupling for driving each cell. The inversion region in the channel directly under the control gate is established directly by a "write or read access" voltage applied to the control gate. The inversion region in the channel directly under the floating gate is established indirectly through the drain and control capacitances and the channel capacitance by the control gate voltage and by another write access voltage applied to the drain.
    Type: Grant
    Filed: September 8, 1980
    Date of Patent: October 18, 1983
    Inventor: Eliyahou Harari
  • Patent number: 4403936
    Abstract: The invention is relating to a press for compressing a powdery material to grains comprising a loosely arranged, rotatable annular, perforated mould supported and guided by a rotatable mould holder and by an axially displaceable supporting member which supports the mould at the end remote from the mould holder, the side face of a mould engaging the mould holder being urged by the supporting member with a given force against the mould holder in the operational position of the press in a manner such that during the operation of the press the mould is caught along by the mould holder owing to the force produced between the mould holder and the mould, whilst a rotatable roller is arranged in the mould whereby an uninterrupted channel is provided at least at the level of the side face of the mould engaging the drivable mould holder.
    Type: Grant
    Filed: May 7, 1981
    Date of Patent: September 13, 1983
    Inventor: Theodorus J. Heesen
  • Patent number: 4404525
    Abstract: An operational amplifier gain stage utilizing switched capacitor resistor equivalent circuits is designed utilizing a delayed clock reference signal (.phi..sub.D, .phi..sub.D) in a unique manner, thereby eliminating the effects of spurious error voltages (E.sub.S) generated when utilizing metal oxide silicon field effect transistors as switches (12, 15, 21, 23, 25). The single remaining MOSFET switch (21) which will contribute a spurious voltage component to the output of the operational amplifier gain stage is designed in such a manner as to minimize the spurious voltage generated during operation of the MOSFET switch. A single dummy switch (31) is utilized to further minimize the spurious voltage generated by this single MOSFET switch.
    Type: Grant
    Filed: March 3, 1981
    Date of Patent: September 13, 1983
    Assignee: American Microsystems, Inc.
    Inventors: Gideon Amir, Yusuf Haque, Roubik Gregorian
  • Patent number: D271584
    Type: Grant
    Filed: February 12, 1981
    Date of Patent: November 29, 1983
    Inventor: David M. Arrigoni