Abstract: An adaptive circuit and method for separating luminance and chrominance components from a composite video signal by deriving three input lines from the composite video signal, determining whether any luminance similarity exists among the three input lines, and then selectively enabling a component filter based on any luminance similarity. If no luminance similarity exists among all three of the input lines, then a subtractive comb filter is enabled to maintain high vertical luminance resolution. If luminance similarity exists among all three of the input lines, then an additive comb filter is enabled. The additive comb filter performs three-line averaging when a high degree of similarity exists among all three consecutive input lines to minimize cross-chroma artifacts on lines that are similar.

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC.

Abstract: A method of determining an internal operating mode of an electronic circuit derives multiple comparison rates from a rate of a master clock input, computes one or more clock ratios of the comparison rates to a rate of a sample rate clock input, and determines whether any of the clock ratios is a valid ratio representing a supported clock configuration. The appropriate internal operating mode is then selected based on the valid ratio. In the illustrative embodiment, a clock autodetect unit uses two trip frequencies to derive at least first and second clock comparison rates. The audio converter can operate in three distinct modes (base, high and quad modes). The base mode is selected when the clock ratio is about 256, the high mode is selected when the clock ratio is about 128, and the quad mode is selected when the clock ratio is about 64. A multiplexer can be used to sequence through the computer clock ratios to ensure that a highest valid ratio is used among a plurality of valid ratios.

Abstract: A rate ½, d=1 channel code encodes a Gray code servo track address into channel data recorded on a magnetic disk; a d=1 Viterbi sequence detector detects the recorded servo track address upon read back; a cost effective d=1 decoder decodes the recorded servo track address into its Gray code representation; and a 1/1+D filter decodes the Gray code track address into its binary representation. The channel encoding scheme increases the data density of the storage system due to the d=1 constraint and use of the Viterbi sequence detector. Further, the implementation advantageously uses the Viterbi sequence detector already provided in a read channel for detecting user data, and the cost and complexity of the decoder is reduced by encoding/decoding the Gray code track address in sections of five bits.

Abstract: A chopping amplifier and method for chopping an input signal are disclosed. The chopping amplifier and method utilize at least two chopping amplifier stages. A chopping operation of an input signal is segmented across two or more chopping amplifier stages, and the two or more chopping amplifier stages are responsive to a master controller. Chop clock signals of the chopping amplifier stages are staggered so that they have non-overlapping periods and at least one of the chopping amplifier stages is not operating in an open loop at any given time. The non-overlapping periods are periodic so that a master chop clock of the master controller can be operated at a lower chop clock frequency. For every doubling of N number of chopping amplifier stages, magnitudes of chopping artifacts and aliased components are each respectively reduced by 3 dB.

Abstract: A method of operating a delta-sigma modulator by providing a variable-level quantizer, which selectively enables an additional quantizer level(s) during a ramp up sequence of the modulator. The additional quantizer level(s) is/are disabled during normal operation. The quantizer truncates a summer output and selectively enables the additional quantizer levels by clipping the truncated sum within a first range of quantizer levels during the ramp up sequence and within a second range of quantizer levels during normal operation in which there are more quantizer levels in the first range than in the second range. The quantizer preferably enables at least two additional quantizer levels at a low end of the quantizer range. For example, the range of quantizer levels for normal operation of the modulator can be from ?6 to +6, while the range of quantizer levels for ramp up operation of the modulator can be from ?8 to +7.

Abstract: A multiprocessor digital amplifier system is disclosed. A first processor is configured to decode a digital signal from a digital signal source. A second processor configured to provide control signals to the first processor. An expansion unit for communicating instructions and data between the processors and a memory device has a first port coupled to the first processor and a second port coupled to the second processor. The expansion unit includes a state generator with circuitry for selecting one of the first and second ports for receiving a memory device access grant. The first and second ports may be granted access in accordance with a selected arbitration protocol. A duration of the memory device access grant selectably constitutes one of a preselected number of accesses and a preselected timeslice. An amplifier amplifies the decoded digital signal from the first processor.

Abstract: A robust Artificial Neural Network controller is proposed for the motion control of a magnetic disk drive voice coil motor (voice coil motor). The neural controller is used to approximate the nonlinear functions (actuator electromechanical dynamics) of the voice coil motor while having on line training. One main advantage of this approach, when compared with standard adaptive control, is that complex dynamical analysis is not needed. Using this design, not only strong robustness with respect to uncertain dynamics and non-linearities can be obtained, but also the output tracking error between the plant output and the desired reference can asymptotically converge to zero. Additionally, standard offline training, utilizing training vectors to stimulate the voice coil motor, is not required.

Abstract: An apparatus and method for limiting the output current in a switched mode amplifier are implemented. The apparatus includes a driver amplifier configurable for selective operation in one of three modes. The amplifier is operable for transitioning between the first mode and one of the second and third modes in response to a state of an output node of the driver. Bias circuitry, configurable for selective coupling to the driver amplifier is operable for limiting the output current of the amplifier in the first operating mode.

Abstract: An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.

Abstract: The present invention includes an intelligent router and method for improving the routing of datagrams, resulting in increased effective bandwidth over networks of high latency. The intelligent router can be used alone or in combination with a second intelligent router. An intelligent router buffers data bound for a destination node within the router itself until the destination node has available space. In addition, the intelligent router of the present invention may continue to transmit a datagram without waiting for confirmation of receipt of a previous datagram. Also, retransmission requests can be ignored until a later time to accommodate for the delay in the network. When using multiple intelligent routers communicating with each other, only the erroneous portions of individual datagrams need to be resent. Routing between two intelligent routers eliminate or reduces the transmission of redundant data being sent.

Abstract: There is a need for low-cost and reliable shock-sensing methods in magnetic hard-disk drives to maintain data integrity when a drive is subjected to external shocks. The present invention uses a novel shock-sensing method that is both reliable and low-cost, using a modified head preamplifier to detect servo fields from adjacent disk surfaces, as well as the disk surface being written or read. Servo fields on adjacent surfaces may be staggered. When a write head is writing data to a data field on a disk surface, a read head may be reading a servo field from an adjacent surface, insuring that the write head is on-track. By staggering the servo fields from surface to surface, shock may be sensed by measuring displacement of read heads on adjacent surfaces between servo sectors on the write surface. In addition, the use of a shock sensor or the like may be eliminated, reducing drive component cost.

Abstract: A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform(DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

Abstract: A Fuzzy Inference System (FIS) algorithm capable of discriminating among various disc types including double-layer DVD, single-layer DVD, CD-ROM/CD-Audio, CD-R, and CD-RW is used to identify disc type in an optical drive. This FIS optical disc determination algorithm relies on the physical properties of the reflecting layer of an optical disc, using a DVD and CD photo diode outputs, to discriminate among several disc types. Focus error and quad sum data from both DVD and CD lasers is provided as eight inputs to a nineteen rule Sugeno FIS which outputs a value corresponding to drive type.

Abstract: A data clock pin SCLK may be used to receive an SCLK signal as well as sleep and reset signals. During normal operation, the SCLK input pin may receive the SCLK signal, a square wave type clock signal. However, the SCLK signal may also be coupled to a one-shot within the device. When signal SCLK is held high for a predetermined period of time, the one-shot is triggered and a SLEEP signal is generated. The device reacts to this SLEEP signal by entering a sleep mode. Similarly, if the SCLK signal is held low for a predetermined period of time, the one-shot may output a low level RESET signal. This RESET signal resets the device into an initial condition state. Other modes of operation, such as test modes and the like may be entered into by holding the SCLK signal high or low in conjunction with a predetermined logic level on another pin (e.g., VREF).

Abstract: A buffer arrangement uses separate amplifiers for handling for positive going signal transitions and for negative going signal transitions respectively. A comparator detects the direction of transition and a switching element connects signal input lines in the appropriate sense to the respective amplifiers based on the output of the comparator. This permits amplifiers optimized for positive or negative going transitions to be used.

Abstract: A portable radio telephone handset operates as a data transfer terminal as well as an analog cellular telephone subscriber station. Two modes of operation, an analog cellular communication mode and a Cellular Digital Packet Data (CDPD) mode, are available in the handset. The handset distinguishes between paging signals indicating CDPD mode communications and those indicating analog cellular communications. The handset also automatically preempts CDPD communications in favor of analog cellular communications such as those carried out in an AMPS configuration. The handset maintains an active status on a CDPD communication channel during a “sleep mode”, when the handset can carry out AMPS activity.

Abstract: Measurement data collected by isolated ADCs in multiple channels may be related. In such a scenario, data may be transmitted to a microcontroller or programmable logic device for centralized processing. Gain and offset of the ADCs in different channels, particularly their drift relative to one another, is an issue which requires attention. In particular, a pair of precision resistors is provided to calibrate the different channels. The ADCs may be factory calibrated and the ratio between the two precision resistors stored within the ADCs. The ADCs may later self-calibrate by comparing their relative gains to the stored resistor ratio. Gain of one of the ADCs may be adjusted relative to the other in order to maintain a relative gain calibration. Although absolute gain is not calibrated (as the resistors are isolated) for particular applications, only relative gain between the ADCs is relevant.

Abstract: The present invention provides an alternative to Prior Art isolation techniques by providing a capacitively coupled reference voltage and a capacitively coupled gain calibration. The isolation technique of the present invention is based upon the idea of a near unity gain capacitive divider. If the load or parasitic capacitance is Cload and the isolation capacitance is Ciso, then the gain between input and output can be calculated as Vout/Vin=(Ciso)/(Ciso+Cload), which will be nearly unity (i.e., 1) when Ciso>>Cload. In addition, if Ciso>>Cload, the gain will also be largely insensitive to variations in Ciso and Cload. For example, if Cin is 100 ppm of Ciso, then a 10% variation in Ciso or Cload results in only a 10 ppm variation in the voltage gain.

Abstract: In a signal processing integrated circuit having a plurality of physical channels and a plurality of gain registers, a plurality of offset registers and an plurality of setup registers, mechanisms are provided to assign one of a plurality of gain registers independently of a selected one of a plurality of offset registers when processing signals from a physical channel.