Abstract: A gain or input volume controller and method includes a modified R2R ladder network having a number of R2R branches, switches coupled respectively to the R2R branches, and a switch controller for respectively controlling the switches to control and provide an overall gain value for a signal. The switch controller further includes a mapper for mapping a gain control signal to the switches wherein the gain control signal respectively activates or deactivates the switches. A fine gain control stage provides a fine gain control of the overall gain value. A coarse gain control stage is coupled to the fine gain control stage. The coarse gain control stage includes the modified R2R ladder network and provides a coarse gain control of the overall gain value.

Abstract: A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.

Abstract: A rate ½, d=1 channel code encodes a Gray code servo track address into channel data recorded on a magnetic disk; a d=1 Viterbi sequence detector detects the recorded servo track address upon read back; a cost effective d=1 decoder decodes the recorded servo track address into its Gray code representation; and a 1/1+D filter decodes the Gray code track address into its binary representation. The channel encoding scheme increases the data density of the storage system due to the d=1 constraint and use of the Viterbi sequence detector. Further, the implementation advantageously uses the Viterbi sequence detector already provided in a read channel for detecting user data, and the cost and complexity of the decoder is reduced by encoding/decoding the Gray code track address in sections of five bits.

Abstract: A chopping amplifier and method for chopping an input signal are disclosed. The chopping amplifier and method utilize at least two chopping amplifier stages. A chopping operation of an input signal is segmented across two or more chopping amplifier stages, and the two or more chopping amplifier stages are responsive to a master controller. Chop clock signals of the chopping amplifier stages are staggered so that they have non-overlapping periods and at least one of the chopping amplifier stages is not operating in an open loop at any given time. The non-overlapping periods are periodic so that a master chop clock of the master controller can be operated at a lower chop clock frequency. For every doubling of N number of chopping amplifier stages, magnitudes of chopping artifacts and aliased components are each respectively reduced by 3 dB.

Abstract: Overlay buffering scheme for multi-channel data in which one memory buffer content is overlayed over another as memory locations of an input buffer are freed when data is output from the input buffer. By overlaying the buffer content, only one input buffer is used, reducing the needed memory by half.

Abstract: An integrated circuit has circuitry and pins coupled to the circuitry. One of the pins is a non-dedicated reset pin having a pin signal that is set at a level outside of a normal range for the pin signal so that the integrated circuit is indicated to reset.

Abstract: A loop filter device and method for a phase locked loop (“PLL”) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes an integral path circuit and a new proportional path circuit cascaded together in series and further includes a summer. The integral path circuit integrates a loop filter input signal to provide an integrated signal that tracks an overall input signal level. The new proportional path circuit differentiates the integrated signal to provide a proportional signal based on a detected instantaneous phase difference for locking a frequency of a signal for a phase locked loop (PLL) circuit to a reference frequency. The summer receives as inputs and sums the integrated signal and the proportional signal to provide a low-noise loop filter output signal.

Abstract: A power on reset circuit, preferably for an integrated circuit, detects application of voltage, starts a phase locked loop one application of voltage is detected but inhibits all clock used for digital logic operations until voltage stability is achieved. If a switched converter is used, the duty cycle of the switched converter is held at unity for a period of time before it is set to that needed to achieve the desired chip operating voltage. Clocks controlling other circuits can be released in stages after the duty cycle of the switched converter is set to its operating voltage level.

Abstract: An integrated circuit and method for indicating the integrated circuit to enter into a scan mode are disclosed. A designated signal, such as an analog supply signal, for an analog block of an integrated circuit is utilized for indicating entry of a digital block of the integrated circuit into a scan mode. Operations of the analog block and the digital block are generally independent from each other during scan mode. Prior to the digital block utilizing the designated signal, voltage rails for the designated signal are resolved with the voltage rails of a digital supply signal for the digital block.

Abstract: In one embodiment of the present invention an apparatus and method is disclosed for recording audio/video information onto a compact disc recorder in real-time. The audio/video information is streamed at a constant rate from a source having an output buffer and so as to prevent overflowing of the output buffer, the streamed audio/video information is received at a constant rate for storage into an input buffer, the streamed audio/video information is for recording thereof onto the compact disc recorder so as to prevent underflowing of the input buffer.

Abstract: The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a low-power mode of operation. A noise invariant circuit disables row skip operation in a multi-row multiplier, to enable analog sampling. Disabling of the row skip operation is accomplished at a time which is several digital cycles preceding the time of analog sampling. Power saving multiplier row skippage resumes after analog sampling is completed.

Abstract: A method of encoding a digital signal, particularly an audio signal, which predicts favorable scalefactors for different frequency subbands of the signal. Distortion thresholds which are associated with each of the frequency subbands of the signal are used, along with transform coefficients, to calculate total scaling values, one for each of the frequency subbands, such that the product of a transform coefficient for a given subband with its respective total scaling value is less than a corresponding one of the distortion thresholds. In an audio encoding application, the distortion thresholds are based on psychoacoustic masking. The invention may use a novel approximation for calculating the total scaling values, which obtains a first term based on a corresponding distortion threshold, and obtains a second term based on a sum of the transform coefficients. Both of these terms may be obtained using lookup tables.

Abstract: Distortion discrimination circuitry for digital radio receivers and corresponding methods are disclosed that accurately and efficiently discriminate distortion events, including impulse noise and multipath distortion events, to improve the quality of audio output signals. The distortion discrimination circuitry monitors and analyzes the demodulator output to determine when a distortion event has occurred and provides an appropriate indication signal for use by other circuitry within the radio receiver. More particularly, the distortion discrimination circuitry includes impulse noise circuitry that looks for high frequency noise in both the magnitude and multiplexed outputs of the demodulator to determine the occurrence of impulse noise distortion events.

Abstract: A method of operating a delta-sigma modulator by providing a variable-level quantizer, which selectively enables an additional quantizer level(s) during a ramp up sequence of the modulator. The additional quantizer level(s) is/are disabled during normal operation. The quantizer truncates a summer output and selectively enables the additional quantizer levels by clipping the truncated sum within a first range of quantizer levels during the ramp up sequence and within a second range of quantizer levels during normal operation in which there are more quantizer levels in the first range than in the second range. The quantizer preferably enables at least two additional quantizer levels at a low end of the quantizer range. For example, the range of quantizer levels for normal operation of the modulator can be from ?6 to +6, while the range of quantizer levels for ramp up operation of the modulator can be from ?8 to +7.

Abstract: An apparatus and method for safely handling asynchronous shutdown of pulsewidth modulated output. A shutdown circuit controls asynchronous shutdown of a pulsewidth modulated stage to ensure that pulsewidth modulated signals of less duration than a minimum period does not occur at transition edges of the pulsewidth modulated signal, in which such short pulses may affect the proper operation of output circuitry.

Abstract: The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a low-power mode of operation. A noise invariant circuit disables row skip operation in a multi-row multiplier, to enable analog sampling. Disabling of the row skip operation is accomplished at a time which is several digital cycles preceding the time of analog sampling. Power saving multiplier row skippage resumes after analog sampling is completed.

Abstract: Techniques related to a digital filter include at least one decimator disposed between an integrator section and a comb section such that the transfer function of the filter has split zeros. The resulting filter implementation employs considerable less silicon real estate than other prior art implementations with spread zeros, and has more design flexibility with improved resulting performance than the Hogenauer implementation.

Abstract: A gain control at the input monitors an input signal and a supply voltage, which drives an output. The gain control adjusts the gain to compress the input signal when the supply voltage decreases in magnitude and/or the input signal is of such magnitude to cause the supply voltage to decrease.

Abstract: A successive-approximation-register (SAR) analog-to-digital converter (ADC) and method utilizing N three-way elements are disclosed. The SAR ADC has a SAR logic system that implements an efficient search algorithm. The search algorithm involves initializing each of N three-way elements of a digital-to-analog converter (DAC) for the SAR ADC to a middle reference voltage. Each of the N three-way elements is able to be set to one of three values: a high reference voltage, a middle reference voltage, or a low reference voltage. The search algorithm determines and sets each of the N three-way elements from the middle reference voltage to either the high reference voltage or the low reference voltage depending upon a comparison result between an analog input value of the SAR ADC and a DAC voltage value.

Abstract: A loop filter device and method for implementing a loop filter for a phase locked loop (“PLL”) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes a proportional path circuit and an integral path circuit. The proportional path circuit receives a charge pump output and determines and holds a charge to be directed to or taken from a PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for a PLL circuit to a reference frequency. The integral path circuit is coupled to the proportional path circuit, and the integral path circuit receives another charge pump output and tracks a total charge level for the PLL circuit based on phase differences for present and prior update periods.