Abstract: A portable communications subscriber unit operates as a data transfer terminal as well as an analog cellular telephone M-ES. Two modes of operation, an analog cellular communication mode and a Cellular Digital Packet Data (CDPD) mode, are available in the subscriber unit. The subscriber unit distinguishes between paging signals indicative of a CDPD mode of communication and those indicative of an analog cellular mode of communication. The subscriber unit automatically preempts CDPD communications in favor of analog cellular communications such as those carried out in an AMPS system. The present inventive method enables the subscriber unit to remain registered in the CDPD communication system using a CDPD “sleep mode” while performing activities on the AMPS system. Another aspect of the present invention facilitates the automatic switching of subscriber unit displays to correspond to the communication system with which the unit is presently communicating.

Abstract: A test mode control unit of an integrated circuit receives and decodes a test mode signal to perform testing of the integrated circuit. Logical AND operations are performed on the decoded test control signal and a test signal. The test signal allows the integrated circuit to toggle between test and non-test modes of operation. In one instance, the toggling allows real time debugging of the integrated circuit when test data outputs of internal signals or states are multiplexed onto a data bus.

Abstract: Two or more pulse width modulation stages, each having progressively higher resolution, are utilized to allow the lower resolution stage or stages to operate at lower clock speeds. Later stages are operated at higher clock speeds and thus a smaller portion of the total pulse width modulation circuit utilizes the higher clock speed. Additionally, later stages operate over smaller time intervals in order to reduce usage of the later stages.

Abstract: The invention provides a method and apparatus for generating delays to shift edges of an EFM data stream from an EFM modulator for a CD-R and CD-RW write encoder. EFM data pulse edges may be delayed in increments of about {fraction (1/32)} Tefm where Tefm is the code rate clock of an EFM data stream output. The delays are generated by a synthesizer running at four times the EFM code rate. The synthesizer may be built using a four-stage ring oscillator. Delays are selectable based upon the write strategy matrix in coarse increments of ¼ T and fine increments of {fraction (1/32)} T. For the coarse delay, the EFM data may be passed through a four stage shift register running at Fsynth, where Tefm=4×Fsynth, allowing for a coarse delay selection of ¼ Tefm.

Abstract: A gain control at the input monitors an input signal and a supply voltage, which drives an output. The gain control adjusts the gain to compress the input signal when the supply voltage decreases in magnitude and/or the input signal is of such magnitude to cause the supply voltage to decrease.

Abstract: Byte synchronization between a bus master and a serial interface or other bus slave is maintained and promptly corrected by using a unique signal, issued by the serial interface, to promptly and unambiguously notify the bus master of a loss of synchronization, followed by prompt resynchronization by the bus master. The serial interface sets a selected indicium in a status register equal to a selected value, when an invalid command is sensed at the interface. The bus master reads the status register and, when the selected indicium has the selected value, promptly resynchronizes the serial interface without further delay.

Abstract: A communication system is disclosed in one embodiment of the present invention to include an encoder circuit responsive to an audio signal for performing compression on the audio signal and adaptive to generate an audio output signal based upon the compressed audio signal, the encoder circuit for sampling the audio signal to generated sampled signals, each sampled signals having a real and an imaginary component associated therewith, each sampled signal having an energy and a phase defined within a current block and each sampled signal being transformed to have a real and an imaginary component, a previous block preceding the current block and a block preceding the previous block, the encoder circuit for calculating the phase of the samples of the current block using the real and the imaginary components of the samples of the previous block and the block preceding the previous block, wherein calculations for determining the unpredictability measure is reduced by avoiding trigonometric calculations of the samp

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a histogram-based automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit and a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

Abstract: The computational load of using a sequencer system and the memory allocation requirements demanded for sequencer operation are reduced in operation with functional models that do not require the services of a sequencer. The computational overhead introduced by the sequencer is reduced, and memory resources for a sequencer are diminished. Functional models that do not require sequencing are created with the same framework as functional models that do require sequencing, while eliminating the sequencer's computational overhead for functional models that do not require sequencing, and allowing functional models that to not require sequencing to be created without allocating the memory required to support the sequencer. Further, both sequenced and un-sequenced functional models coexist in the same sequenced verification framework, permitting the un-sequenced functional models to avoid the computational and memory allocation overhead otherwise incurred by the sequencer.

Abstract: A digital-to-analog converter (DAC) output stage has an operational amplifier, an integrating path, a direct or data path, and a differentiated path. The integrating path is coupled in parallel to the operational amplifier. Each of the ends of the integrating path is respectively coupled to an input and an output of the operational amplifier. The direct or data path samples data during a first time sampling phase and is coupled in parallel with the integrating path during a second time sampling phase. The differentiated path is coupled in series with a data input voltage to the input of the operational amplifier.

Abstract: A method and system for integrating a mismatch noise shaper into the main loop of a delta-sigma modulator are disclosed. The mismatch noise shaper output is fed back to the summer and is responsive to the mismatch noise shaper. At appropriate times, the mismatch noise shaper selectively overrides the quantizer so that the mismatch noise shaper changes output values of the mismatch noise shaper from values representative of a corresponding output value of the quantizer to other values representative of a different output value of the quantizer. The overriding feature distinguishes the present Invention from a DEM, as the output of a DEM is only a reordering of the same number of elements as its input. The mismatch noise shaper selectively overrides the quantizer when the quantizer output has prevented the mismatch noise shaper from controlling selection of elements at the mismatch noise shaper output for a predetermined time period.

Abstract: An event sequencer for a functional mechanism contains a list of signatures and corresponding priority designations, and an event list containing event information from race condition events that are to be re-ordered. A method for sequencing race condition events, includes storing signatures for identifying predetermined events, storing priority designations corresponding to the signatures to enable identification of relative priorities between identified events, detecting at least first and second events and information about each event, storing only upon signature match the events and event information associated with each event, sorting the events, and sending the sorted events to a functional mechanism. Events are compared with stored signatures, and signature matches are determined. The arrival of events is detected, events are compared with stored signatures, and matches between events and signatures are established.

Abstract: A processing system for a charge coupled device (CCD) or CMOS imaging system includes a multi-mode, multiple current level, correlated double sample and variable gain (CDS/VGA) circuit for receiving data from a CCD system, subject to horizontal and vertical timing signals for the system which are locally generated by the processing system itself. The processing system particularly includes programmable timing circuitry for controlling the detection of pixel intensity values from elements of a two-dimensional pixel array, with a programable low-frequency master vertical timing circuit driving a high-frequency horizontal timing circuit, wherein the vertical and horizontal timing signals are independently locally provided to the array from the analog processor actually sampling the array. The architecture of the processing system further includes a correlated double sampler, a black level clamp, and an A/D conversion module.

Abstract: A multiprocessor digital amplifier system is disclosed. A first processor is configured to decode a digital signal from a digital signal source. A second processor configured to provide control signals to the first processor. An expansion unit for communicating instructions and data between the processors and a memory device has a first port coupled to the first processor and a second port coupled to the second processor. The expansion unit includes a state generator with circuitry for selecting one of the first and second ports for receiving a memory device access grant. The first and second ports may be granted access in accordance with a selected arbitration protocol. A duration of the memory device access grant selectably constitutes one of a preselected number of accesses and a preselected timeslice. An amplifier amplifies the decoded digital signal from the first processor.

Abstract: A gain characteristic correctable dynamic range enhancement system (DRES) receives input signals from an imager device connected to a correlated double sampling (CDS) circuit for receiving the video signal from the CCD imaging device. The dynamic range enhancement system includes a variable gain amplifier (VGA), and a limited bit-width analog-to-digital converter (ADC) which digitizes the analog signal received from the VGA. The output of the ADC is provided to an initial bit range position of a wider bit-width shifter connected to the output of the ADC. The DRES system correctably extends the dynamic range of the imager device, subject to offsets providing linearity corrections at predetermined trip points, subject to determined offset values, to ensure that there are no discontinuities in the system transfer function.

Abstract: Energy expenditure is reduced in a wireless subscriber station operating in a Cellular Digital Packet Data (CDPD) system by deleting the operation of decoding the Forward Error Correction (FEC) blocks. The decoding of the FEC blocks can be deleted by virtue of using opening and closing Temporary Equipment Identifier (TEI) messages having a minimum hamming distance from all the other TEI messages. Base Error Rate (BER) is measured to determine when the necessity of decoding an FEC block exists. By limiting this operation, battery life for wireless subscriber stations is prolonged.

Abstract: Stereo recovery circuitry for a digital receiver is disclosed that provides increased accuracy and efficiency in recovering stereo signal information from transmitted stereo signals. The stereo decoder includes a digitally controlled oscillator that recovers a pilot tone signal from transmitted stereo signal information. By processing demodulated stereo signals on the digital side and digitally controlling the oscillator, the stereo decoder has increased efficiency and accuracy. In one embodiment, the oscillator may be a phase-locked-loop having a loop filter and an amplitude stabilized tunable resonator. Additional circuitry is disclosed for utilizing the pilot tone signal to recover left and right channel signal information from the demodulated stereo signals.

Abstract: A loop filter device and method for implementing a loop filter for a phase locked loop (“PLL”) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes a proportional path circuit and an integral path circuit. The proportional path circuit receives a charge pump output and determines and holds a charge to be directed to or taken from a PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for a PLL circuit to a reference frequency. The integral path circuit is coupled to the proportional path circuit, and the integral path circuit receives another charge pump output and tracks a total charge level for the PLL circuit based on phase differences for present and prior update periods.

Abstract: A processing system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA) having amplifiers of selectable current level to enable reduced data resolution in a preview display, a low power mode analog-to-digital converter (ADC) having a selectable narrow bit-width output and coupled to said VGA circuit, and a gain circuit coupled to said ADC. The single chip low-power analog front end produces digitized CCD data in either 13-bit, 12-bit or 10-bit formats at a first current level and 9-bit, 8-bit, or 6-bit formats at a second current level. The VGA amplifier includes symmetrical subcircuits which are independently actuable to enable full or reduced data resolution levels respectively for still image capture operation and video previewing on a separate preview screen.

Abstract: Power available to an amplifier is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing could normally occur and relatively low power is provided during another phase. Increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in particular interval. A control circuit provides switching of the current mirrors in a way which minimizes disruption of amplifier operation.