Abstract: An integrated circuit has circuitry and pins coupled to the circuitry. One of the pins is a non-dedicated reset pin having a pin signal that is set at a level outside of a normal range for the pin signal so that the integrated circuit is indicated to reset.

Abstract: A loop filter device and method for a phase locked loop (“PLL”) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes an integral path circuit and a new proportional path circuit cascaded together in series and further includes a summer. The integral path circuit integrates a loop filter input signal to provide an integrated signal that tracks an overall input signal level. The new proportional path circuit differentiates the integrated signal to provide a proportional signal based on a detected instantaneous phase difference for locking a frequency of a signal for a phase locked loop (PLL) circuit to a reference frequency. The summer receives as inputs and sums the integrated signal and the proportional signal to provide a low-noise loop filter output signal.

Abstract: A power on reset circuit, preferably for an integrated circuit, detects application of voltage, starts a phase locked loop one application of voltage is detected but inhibits all clock used for digital logic operations until voltage stability is achieved. If a switched converter is used, the duty cycle of the switched converter is held at unity for a period of time before it is set to that needed to achieve the desired chip operating voltage. Clocks controlling other circuits can be released in stages after the duty cycle of the switched converter is set to its operating voltage level.

Abstract: An integrated circuit and method for indicating the integrated circuit to enter into a scan mode are disclosed. A designated signal, such as an analog supply signal, for an analog block of an integrated circuit is utilized for indicating entry of a digital block of the integrated circuit into a scan mode. Operations of the analog block and the digital block are generally independent from each other during scan mode. Prior to the digital block utilizing the designated signal, voltage rails for the designated signal are resolved with the voltage rails of a digital supply signal for the digital block.

Abstract: In one embodiment of the present invention an apparatus and method is disclosed for recording audio/video information onto a compact disc recorder in real-time. The audio/video information is streamed at a constant rate from a source having an output buffer and so as to prevent overflowing of the output buffer, the streamed audio/video information is received at a constant rate for storage into an input buffer, the streamed audio/video information is for recording thereof onto the compact disc recorder so as to prevent underflowing of the input buffer.

Abstract: The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a low-power mode of operation. A noise invariant circuit disables row skip operation in a multi-row multiplier, to enable analog sampling. Disabling of the row skip operation is accomplished at a time which is several digital cycles preceding the time of analog sampling. Power saving multiplier row skippage resumes after analog sampling is completed.

Abstract: A method of encoding a digital signal, particularly an audio signal, which predicts favorable scalefactors for different frequency subbands of the signal. Distortion thresholds which are associated with each of the frequency subbands of the signal are used, along with transform coefficients, to calculate total scaling values, one for each of the frequency subbands, such that the product of a transform coefficient for a given subband with its respective total scaling value is less than a corresponding one of the distortion thresholds. In an audio encoding application, the distortion thresholds are based on psychoacoustic masking. The invention may use a novel approximation for calculating the total scaling values, which obtains a first term based on a corresponding distortion threshold, and obtains a second term based on a sum of the transform coefficients. Both of these terms may be obtained using lookup tables.

Abstract: Distortion discrimination circuitry for digital radio receivers and corresponding methods are disclosed that accurately and efficiently discriminate distortion events, including impulse noise and multipath distortion events, to improve the quality of audio output signals. The distortion discrimination circuitry monitors and analyzes the demodulator output to determine when a distortion event has occurred and provides an appropriate indication signal for use by other circuitry within the radio receiver. More particularly, the distortion discrimination circuitry includes impulse noise circuitry that looks for high frequency noise in both the magnitude and multiplexed outputs of the demodulator to determine the occurrence of impulse noise distortion events.

Abstract: An apparatus and method for safely handling asynchronous shutdown of pulsewidth modulated output. A shutdown circuit controls asynchronous shutdown of a pulsewidth modulated stage to ensure that pulsewidth modulated signals of less duration than a minimum period does not occur at transition edges of the pulsewidth modulated signal, in which such short pulses may affect the proper operation of output circuitry.

Abstract: The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a low-power mode of operation. A noise invariant circuit disables row skip operation in a multi-row multiplier, to enable analog sampling. Disabling of the row skip operation is accomplished at a time which is several digital cycles preceding the time of analog sampling. Power saving multiplier row skippage resumes after analog sampling is completed.

Abstract: Techniques related to a digital filter include at least one decimator disposed between an integrator section and a comb section such that the transfer function of the filter has split zeros. The resulting filter implementation employs considerable less silicon real estate than other prior art implementations with spread zeros, and has more design flexibility with improved resulting performance than the Hogenauer implementation.

Abstract: A gain control at the input monitors an input signal and a supply voltage, which drives an output. The gain control adjusts the gain to compress the input signal when the supply voltage decreases in magnitude and/or the input signal is of such magnitude to cause the supply voltage to decrease.

Abstract: A successive-approximation-register (SAR) analog-to-digital converter (ADC) and method utilizing N three-way elements are disclosed. The SAR ADC has a SAR logic system that implements an efficient search algorithm. The search algorithm involves initializing each of N three-way elements of a digital-to-analog converter (DAC) for the SAR ADC to a middle reference voltage. Each of the N three-way elements is able to be set to one of three values: a high reference voltage, a middle reference voltage, or a low reference voltage. The search algorithm determines and sets each of the N three-way elements from the middle reference voltage to either the high reference voltage or the low reference voltage depending upon a comparison result between an analog input value of the SAR ADC and a DAC voltage value.

Abstract: A loop filter device and method for implementing a loop filter for a phase locked loop (“PLL”) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes a proportional path circuit and an integral path circuit. The proportional path circuit receives a charge pump output and determines and holds a charge to be directed to or taken from a PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for a PLL circuit to a reference frequency. The integral path circuit is coupled to the proportional path circuit, and the integral path circuit receives another charge pump output and tracks a total charge level for the PLL circuit based on phase differences for present and prior update periods.

Abstract: A portable communications subscriber unit operates as a data transfer terminal as well as an analog cellular telephone M-ES. Two modes of operation, an analog cellular communication mode and a Cellular Digital Packet Data (CDPD) mode, are available in the subscriber unit. The subscriber unit distinguishes between paging signals indicative of a CDPD mode of communication and those indicative of an analog cellular mode of communication. The subscriber unit automatically preempts CDPD communications in favor of analog cellular communications such as those carried out in an AMPS system. The present inventive method enables the subscriber unit to remain registered in the CDPD communication system using a CDPD “sleep mode” while performing activities on the AMPS system. Another aspect of the present invention facilitates the automatic switching of subscriber unit displays to correspond to the communication system with which the unit is presently communicating.

Abstract: A test mode control unit of an integrated circuit receives and decodes a test mode signal to perform testing of the integrated circuit. Logical AND operations are performed on the decoded test control signal and a test signal. The test signal allows the integrated circuit to toggle between test and non-test modes of operation. In one instance, the toggling allows real time debugging of the integrated circuit when test data outputs of internal signals or states are multiplexed onto a data bus.

Abstract: Two or more pulse width modulation stages, each having progressively higher resolution, are utilized to allow the lower resolution stage or stages to operate at lower clock speeds. Later stages are operated at higher clock speeds and thus a smaller portion of the total pulse width modulation circuit utilizes the higher clock speed. Additionally, later stages operate over smaller time intervals in order to reduce usage of the later stages.

Abstract: A gain control at the input monitors an input signal and a supply voltage, which drives an output. The gain control adjusts the gain to compress the input signal when the supply voltage decreases in magnitude and/or the input signal is of such magnitude to cause the supply voltage to decrease.

Abstract: Byte synchronization between a bus master and a serial interface or other bus slave is maintained and promptly corrected by using a unique signal, issued by the serial interface, to promptly and unambiguously notify the bus master of a loss of synchronization, followed by prompt resynchronization by the bus master. The serial interface sets a selected indicium in a status register equal to a selected value, when an invalid command is sensed at the interface. The bus master reads the status register and, when the selected indicium has the selected value, promptly resynchronizes the serial interface without further delay.

Abstract: A communication system is disclosed in one embodiment of the present invention to include an encoder circuit responsive to an audio signal for performing compression on the audio signal and adaptive to generate an audio output signal based upon the compressed audio signal, the encoder circuit for sampling the audio signal to generated sampled signals, each sampled signals having a real and an imaginary component associated therewith, each sampled signal having an energy and a phase defined within a current block and each sampled signal being transformed to have a real and an imaginary component, a previous block preceding the current block and a block preceding the previous block, the encoder circuit for calculating the phase of the samples of the current block using the real and the imaginary components of the samples of the previous block and the block preceding the previous block, wherein calculations for determining the unpredictability measure is reduced by avoiding trigonometric calculations of the samp