Abstract: Flexible VLSI architecture implements of MPEG video processing unit (VPU) for encoding and decoding. In encoding mode, VPU performs compression operations on digitized video input per MPEG standard; and in decoding mode, VPU performs decompression operations on video bitstream per MPEG standard. VPU modules include: Discrete Cosine Transformation (DCT), Inverse Discrete Cosine Transformation (IDCT), Quantization (QNT), Inverse Quantization (IQ), Variable Length Encoding (VLC), Variable Length Decoding (VLD) and Motion Compensation (MC). VPU functions in half duplex, and hardware modules are shared between encode/decode modes. Architecture provides low-cost, flexible and efficient solution to implement real-time MPEG codec. Specific system configuration is not required, and general interface supports various operating conditions.

Abstract: A phase lock loop is provided for recovering timing information from a received data signal in a 100Base-TX receiver. The phase lock loop includes a phase encoder (803) for generating a reference phase error. An output phase value on a bus (809) is subtracted from the reference phase value on line (805) with a subtraction block (813) to generate a phase error. This phase error is averaged and decimated over a predetermined number of potential symbol transitions in the received signal. The output phase error is provided from a block (815) on a line (817) to a loop filter. This output is provided only once for each decimation operation such that the loop filter can operate at a lower clock rate. The phase error output is then utilized to select one of multiple clocks that correspond to the phase error, these being incremental phase clocks referenced to a master clock. This utilizes a clock multiplexer (1427) to select one of the multiple clock inputs which are delayed in phase off of the master clock.

Abstract: An analog multiplier or mixer that mixes a signal fc with a square wave local oscillator improves heterodyning operation of a circuit. In various square wave analog multiplier or mixer embodiments, heterodyning performance is improved in noise reduction, saturation performance, linearity, and other measures by adding a DC current path in parallel to a signal current path of the multiplier or mixer. The parasitic capacitances, noise, and nonlinearity problems in a heterodyning circuit are solved by adding a path to a square wave mixer for carrying the signal current and the DC current on different paths. An apparatus includes a circuit coupled between a first voltage reference and a second voltage reference. The circuit includes a first square wave oscillator branch and a second square wave oscillator branch. The first square wave oscillator branch is driven by a square wave oscillator signal and the second square wave oscillator branch is driven by an inverse of the square wave oscillator signal.

Abstract: Defect management for automatic track processing without an ID field, processes defect information for a track on a magnetic media within a disk drive system. A system which uses any method of defect management including linear replacement, sector slipping, cylinder slipping or segment slipping, can be supported. A physical sector number for each sector is translated to a logical sector number relating to the order of data on a track. This translation of the physical sector number to a logical sector number for automatic track processing can be accomplished using any one of three methods: 1) a track defect table can be built in the buffer RAM; 2) the defect information can be written in the header of every sector; or 3) a system FIFO, located in the onboard logic, can be used to manage the defect list. In the second method, the header subfield comprises four defect records.

Abstract: A multi-path unity gain buffer circuit and method are implemented in a slew amplifier. The multi-path unity buffer has a high frequency signal path and a low frequency signal path. The high frequency signal path has a differential amplifier powered for providing a high frequency, low accuracy buffering operation. The low frequency signal path is coupled to the high frequency signal path. The low frequency signal path has an operational amplifier powered to provide a low frequency, high bandwidth buffering operation. An output of the operational amplifier is fed back to an input of the operational amplifier through a current varying element that varies current levels of the input of the operational amplifier to remove a level shift of an output signal of the differential amplifier.

Abstract: A serial interface or port is configured so that: a Read command and a Write command can be performed substantially simultaneously; a shortened Read command, followed by another Read command, can be performed in reduced time, due to the shortening of the first Read command; and a continuous stream of Read commands can be performed consecutively with no time delay By performing Read and Write commands simultaneously on associated channels at a serial interface, the time required for such performance is reduced by as much as 50 percent.

Abstract: A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system further includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value.

Abstract: A stress test circuit and method for static random access memory (“SRAM”) cells of an SRAM device are disclosed. The stress test component has a resistance element and a switch component to electrically couple the resistance element between a bit line and complementary bit line of an SRAM cell storing a digital value. Stress test component is activated to electrically couple the resistance element to the bit line and complementary bit line. An electrical path is created causing a voltage on an SRAM circuit path maintaining the digital value to be pulled in one direction by a stress current. The electrical path causes another voltage on another SRAM circuit path maintaining a complementary digital value to be pulled in an opposite direction by the stress current. The SRAM cell is then read to determine whether the digital value has changed state.

Abstract: A method and system for selecting implementation of a filter controller between a single conversion that ensures a fully-settled converted output and a continuous conversion of an input signal are disclosed. State machine determines whether convert start signal has a duration, which ends on or before a first occurrence of a conversion done on the input signal. Conversion done is an occurrence of when a bit set has been converted from the input signal. If convert start signal has a duration which ends on or before the first occurrence of conversion done, then state machine selects and implements single conversion of the input signal. Digital system ensures a fully-settled converted output by waiting for the filter to receive and filter a predetermined number of bit sets for a conversion output and then outputting the conversion output. Otherwise, state machine selects and implements continuous conversion of the input signal.

Abstract: A communication integrated circuit, such as a full-duplex speakerphone circuit, includes a double-talk detector that operates in combination with an echo canceller. The echo canceller includes an adaptive filter with filter coefficients that are regularly adjusted to train to a received echo. The double-talk detector includes an ERLE detector for measuring the current ERLE of the echo canceller and a logic circuit for determining a best ERLE value over a plurality of measurements. The double-talk detector also includes a power estimator and noise estimator for determining a noise level. The noise level attained when the ERLE value is the best ERLE value is saved as a benchmark noise level. Filter coefficients of the echo canceller are updated or updating is blocked based on several considerations including a comparison of ERLE value to best ERLE value, the noise level in comparison to the benchmark noise level, whether the circuit is operating in half-duplex or full-duplex mode, and detection of a tone.

Abstract: A method and device to synchronize sampled digital data transferred from an input section to an output section prevents data overrun or underrun due to timing differences of timing signals of the input and output section. The timing synchronization device has an input sampled data counter to determine a number of samples in a frame time of the input sampled data. The timing synchronization device further has an interpolator to estimate data sample values for each sample of the input sampled data to coincide with each sample of the output sampled data if the number of samples in said input sampled data is less than an expected number of samples in said output sampled data.

Abstract: An analog to digital converter system includes first and second delta sigma converters, a calculation engine, and a serial interface on a single chip. The calculation engine is configured to calculate energy, power, rms current and voltage for single phase 2 or 3 wire power meters. Voltage and current are measured with a shunt or transformer, and a divider or transformer, respectively. The serial interface is bidirectional for communication with a microprocessor or controller, and provides a fixed width programmable frequency output proportional to energy. The digital converter system is user system calibratible.

Abstract: A method and system are disclosed for operating two or more integrator amplifiers with different power supplies for a modulator of an analog-to-digital (“A/D”) converter. A first, upstream integrator is operated with one power supply, and the other downstream integrator(s) is/are operated with at least another power supply. The modulator has amplifiers with coefficient gains having values that are determined and set so that voltage levels for the at least another integrator are maintained within operating and output limits. An integrating coefficient gain k1 for the first integrator is set to have a sufficiently large value so that an integrating capacitor can be made small for the one integrator. Another integrating coefficient gain k2 for a second integrator is set to have a sufficiently small value so that an output voltage from the first integrator is sufficiently attenuated to a voltage value within an operating range of the second integrator.

Abstract: Station scan circuitry for a radio-frequency receiver and corresponding methods are disclosed that efficiently determine the presence of a station on available channels. The station scan circuitry includes circuitry that determines if the signal power on a given channel exceeds a threshold value. Additional circuitry compares the channel signal strength and the adjacent channel signal to determine if a ratio of the two exceeds a threshold level. If both the signal power and the signal strength ratio are sufficient, the station scan circuitry indicates that a station has been found. To make the signal strength comparison, the station scan circuitry includes circuitry for determining a post-filter signal strength and a pre-filter signal strength for the received signal.

Abstract: A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system filter includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value.

Abstract: A method and system of operating dynamic element matching (“DEM”) components of a DEM system with two or more power supplies are disclosed. A connection system of the DEM system is driven with one power supply operating at one voltage. Connection system couples to components that are to be matched and equalized in usage by ordering outputs to components and activating the components according to ordered outputs. A connection calculator of the DEM system is driven with another power supply operating at another voltage different from the one voltage. Connection calculator is coupled to the connection system, and connection calculator calculates an order of usage of components. A level shifter system level shifts voltage levels of signals from connection system to connection calculator, and another level shifter system level shifts voltage levels of signals from connection calculator to connection system.

Abstract: A method of processing a stream of audio information received by a multiple processor audio decoder. Processing operations are performed by a first processor on the stream of audio information to produce at set of results. The first processor writes the set of results into a shared memory and a flag is set indicating that the results are ready. In response to the flag, a second processor reads the results from shared memory. When the results have been read from shared memory, the second processor sends a command to the first processor. The first processor then clears the flag.