Abstract: A high voltage input pad and method for accepting electrostatic discharge (ESD) surges without damage to an input semiconductor amplifier. The protection system includes a metal gate, transistor, and n-well resistors which provide ESD protection. Protection is further provided against large voltages coupled to an amplifier by connecting an input bipolar junction transistor to the negative input connection of the amplifier. Negative surges are directed to ground with an anode grounded diode connected at its cathode to the negative input connection of the amplifier.

Abstract: A supplemental echo suppressor controls the attenuators in a transmit path and receive path to selectively set the attenuations based on the signal received from the far-end and the signal transmitted from the near-end. The attenuation levels are set to allow full-duplex communication. If both ends supply speech signals simultaneously, the attenuation is reduced, increasing the clarity of signals at both ends. Attenuation levels are also set when both ends are idle. If, however, the far-end user is talking and the near-end user is silent, and the echo at the near-end is low, then the attenuation is set high. Signal parameters are generated and monitored to control echo suppression. Suppression attenuation decisions are determined on the basis of normalized power estimates that are normalized to a background power estimate that is indicative of background noise. The power and noise parameters are used to determine engagement and disengagement of the suppressors.

Abstract: A modem interface communicates data between a computer and a modem that is coupled to an external communication network. The modem interface includes a host interface for coupling to a host processor of the computer, an analog interface for coupling to the modem, and a digital signal processor for processing the data communicated with the modem and the host processor. A memory is coupled to the host interface, the digital signal processor and the analog interface. The analog interface provides clock signals and converts data between analog and digital for communicating between the memory and the modem. The analog interface provides an interrupt to the digital signal processor to control the transfer of data from the digital signal processor and the memory. The modem interface processes data at sampling rates while the host processor processes data at rates less than the sampling rate of the analog interface.

Abstract: A system and method for selectively providing high pass filtering of two digital signals that are to be subsequently combined. Each of the first and second signals is passed through one of a high pass filter, an all-pass filter and a module that performs substantially no signal filtering, where the phase and magnitude for either high pass filter are substantially equal to the phase and magnitude for either all-pass filter. At the minimum, the system provides the following filtering combinations for the respective first signal and second signal: (no filter, no filter), (high pass, high pass), (high pass, all-pass) and (all-pass, high-pass). Suitable first order high pass and corresponding all-pass filters are determined.

Abstract: A multi-bit DAC (109) is provided as part of a digital-to-analog data converter (DAC). The multi-bit DAC is comprised of a plurality of single-bit DACs (503) which have the values thereof selected through a digital encoder (505). The digital encoder (505) performs dynamic element matching (DEM) on an input data value. The sequence of selection is performed such that the element mismatch noise response of the DAC (109) is shaped. The outputs are summed at a summing junction (507) and then filtered with a low pass filter (113). In the noise shaping response, a cyclical second order response is provided with a Data Weighted Averaging (DWA) technique wherein the outputs of the DACs are restricted to one of two states. To achieve this, select ones of the output values are changed in order to comply with this restriction, thus deviating from a uniform element selection algorithm. This provides a constrained second order response which accounts for mismatching of the DAC elements (503).

Abstract: A graphics processor is disclosed that renders polygons with specular highlighting (glare) based on specular fractional values included in a texture map as components of each texel in the texure map. Each texel in the texture map includes red, green, and blue color values and the specular fractional component. The specular fractional component determines the proportion or percentage of a specular color value that is to be combined with the texel color values. The graphics processor preferably comprises a texture map engine that includes multiplier logic and adder logic. The texture map engine receives three values preferably from a video memory device—the texel color value, the specular fractional component value, and the specular color value. The multiplier multiplies the specular fraction by the specular color value and the resulting product is added to the texel color value. The output value from the adder is then used to render a screen pixel or is provided to another lighting stage.

Abstract: A method and system to use a standard cell function library to automatically configure gate array cells in an integrated circuit layout is provided. A standard cell netlist at the transistor level is compiled to list the transistors required in implementing the desired functions. Based on the netlist, gate array cells are restructured so that they can be inserted in locations designed for standard cells. The restructured gate array cells, which are made up of single poly and double poly structures, are strategically placed in a layout. Using the function net connectivity patterns from the standard cell function library, the gate array cells are connected to implement desired logic functions.

Abstract: The present invention provides a computerized database comprising a first table representing a list of part numbers. The database provides computerized links between individual part numbers and associated manufacturing process data for different process steps for that part number. Rather than correlate data by hand, a user may click on a process step for a particular part number to instantly and accurately retrieve that data. Manufacturing process data may include, for example, backgrind process data, wire binding data, either in numerical or graphical form, testing parameters, packaging data, and labeling data. The database system of the present invention may be used to automatically program various process equipment in an assembly facility with appropriate process data to automatically process finished semiconductor wafers into packaged semiconductor circuits.

Abstract: A multistage comparator is calibrated to remove quasi-autozero voltages derived from the native comparator offset and autozero switch charge injection offsets. A multistage comparator includes a plurality of series connected amplifiers each having a programmable source, and further including a latch. A calibration method for a multistage comparator includes calibrating the first of a series of amplifiers first for both voltage offset and charge injection errors thereby to remove the quasi-autozero voltage and charge injection offsets.

Abstract: A method of processing a stream of audio information received by a multiple processor audio decoder. Processing operations are performed by a first processor on the stream of audio information to produce at set of results. The first processor writes the set of results into a shared memory and a flag is set indicating that the results are ready. In response to the flag, a second processor reads the results from shared memory. When the results have been read from shared memory, the second processor sends a command to the first processor. The first processor then clears the flag.

Abstract: A front end for capturing seismic signals uses a voltage doubling circuit and an analog to digital converter (ADC) having different power levels available during respective operational phases. Power available the ADC is controlled so that relatively high power is provided during one phase of operation, such as during an interval when slewing in a device is expected and relatively low power is provided during another phase. Increased power is provided by switching in parallel current mirrors when power demands are expected to be high, whether or not high power is actually needed in a particular interval. A large step size is selected for the ADC to reduce power consumption for a delta sigma modulator used in the ADC and feedback coefficients are optimized for low power by running at a higher oversampling rate than required by signal to quantization noise requirements.

Abstract: A multiply add carry (MAC) circuit correctly determines the value of a carry bit when an operation X*Y+Z is undertaken, where X, Y and Z are real numbers and where an accumulator and rounding are utilized. The circuit (1) determines if the product X*Y is negative, (2) determines if the value in the accumulator is negative, (3) determines if a round bit propagates all the way to the most significant bit (MSB) position, (4) determines if the result X*Y+Accumulator+round is negative; and (5) determines a correct carry bit based on the other determinations.

Abstract: An sample rate converter for non-audio AES data channels is presented. Channel status (C) information is transferred in 192-bit blocks. Access to received C channel data blocks is allowed, before the blocks are re-transmitted at the output sample rate. This enables users to modify the data, alleviating the effect of data loss caused by different input and output sample frequencies. For U channel status information, U channel status information is transferred as 2×192 bit blocks like the channel status (C) scheme above, as individual information units (IUs), or as messages consisting of 129 IUs. In the latter 2 schemes, the lengths of output inter-IU filler segments or output intemessage filler segments are varied relative to the lengths of inputs inter-IU filler segments or input inter-IU message segments respectively, to compensate for the difference between the input sample frequency and the output sample frequency.

Abstract: An asynchronous sample rate converter for converting a first sample rate in a signal to a second sample rate in the same signal is presented. The signal is first provided as input to an interpolator which upsamples the signal to form a signal having sample rate UFs1 where the upsampling factor U is a variable that is directly related to the ratio Fs2/Fs1. The resampler then linearly interpolates the upsampled signal to form a signal having sample rate DFs2. Finally, the resampled signal is downsampled to form a signal having sample rate Fs2.

Abstract: A method for dynamically caching display list information to an internal on-chip cache performs UV title read hit comparisons to determine whether to read display list parameters from internal cache or external memory.

Abstract: User adjustable weight device 10 is worn by a user for applying weight to the user. Weight device 10 comprises a strap portion 12 and weight roll pockets 14. Rolls of weights 16 are inserted into and removed from the weight roll pockets 14 so that a desired amount of weight is controlled, adjusted, and achieved by the user as desired. Weight device 10 further has a fluid containing device 24 with a fluid inlet 26. Fluid containing device 24 receives and holds fluid filled by the user through the fluid inlet 26. Fluid is filled into or removed from the fluid containing device 24 so that a desired amount of weight is controlled, adjusted, and achieved by the user as desired. An audio unit 30 is coupled to the strap portion 12 wherein the audio unit 30 is able to play and/or record information. A storage pocket 40 is coupled to the strap portion 12 wherein the storage pocket 40 stores various items.

Abstract: A method and system for filtering texture map data for improved image quality in a graphics computer system. The present invention is directed to a method and system for performing texture map filtering for reducing “flickering” and “sparkling” when rendering a relatively small graphics primitives using a texel map of relatively larger area and low color frequency. A footprint area is defined as the area of texel map space that is mapped into one pixel coordinate of display space. One embodiment of the present invention is particularly useful in texture mapping where the footprint area is larger than one. In this instance, during rendering, the change in texel map coordinates (e.g., du, dv) is large for a unit change in screen coordinates (e.g., dx, dy). When obtaining a texel at location (u, v), the present invention performs a color filtering of texels located at distances du and dv away from the texel at location (u, v).

Abstract: A new embodiment LED traffic light 40 having a housing 49 that provides at least three signal lights 42, 44, and 46. The three signal lights 42, 44, and 46 are all embedded in a single opening 50 of housing 49. The LEDs for signal lights 42, 44, and 46 are arranged in a generally common area that allows activation and display of one of the signal lights in a corresponding symbolic shape (i.e. universal symbol or words). Red signal light 42 has red LEDs 41 spread out and arranged in an octagon shape (i.e. stop sign shape). From a distance or afar, however, it may be difficult for persons to distinguish between the octagon shape and the circular shape (i.e. stop and go signals respectively). Therefore, a border 52 of contrasting color LEDs 54 (i.e. different color other than the color of the octagon) is placed around the octagon shape and illuminated to further enhance and define the stop sign or octagon shape thereof. The border 52 may be made to blink or flash (i.e. by blinking all of the LEDs 54).

Abstract: An adjustable and portable table 10 with improved foldable leg assembly 20. The leg assembly 20 supports a table surface 12. The leg assembly 20 includes a mounting bar 18, a first angled leg component 40, and a second angled leg component 40. The second leg component 40 is able to rotate relative to at least a portion of the mounting bar 18 so that the second leg component 40 is out of a way of the first leg component 40 when the first and second leg components are being folded to the storage position. The first and second leg components 40 are able to be unfolded to a usable position. The mounting bar 18 further has a first bar portion 24 to which the first leg component 40 is coupled and a second bar portion 26 to which the second leg component 40 is coupled. The second bar portion 26 rotates relative to the first bar portion 24. The first bar portion 24 and the second bar portion 26 are able to be placed in rotational lock and unlock positions.

Abstract: Apparatus 10 uses presently existing, conventional extension cord(s) 40 to couple a power tool 20, which normally operates using an internal direct current power source (i.e. battery cartridge), to an external direct current power source 90. The apparatus 10 has a power tool adapter or coupler 30 that couples to the power tool 20 and that further couples to a plug end of the extension cord(s) 40. The apparatus 10 also has an external source adapter or coupler 50 that couples to the other plug end of the extension cord(s) 40 and that further couples to the external direct current power source 90. The power tool adapter or coupler 30 has a tool adapter housing/casing 32 or battery cartridge housing/casing 32 that is conformed to slidingly insert, fit, and couple into a power source receptacle 22 of the power tool 20. A safety trip mechanism or fuse 70 is integrated into the power tool adapter or coupler 30 to prevent damage and injury when a power overload or surge occurs.