Abstract: A FIFO is operated so no changes occur on an output thereof in response to (1) only one stage of the FIFO having a signal stored therein when a read command is supplied to the FIFO exclusively of a write command and/or (2) the FIFO being flushed, i.e., erased. Result (1) is achieved by decrementing a write pointer by one without changing a read pointer or by loading the write pointer with the contents of the read pointer. Result (2) is achieved by loading the write pointer with the contents of the read pointer.

Abstract: Phase compensation in a dual-channel analog-to-digital converter (ADC) is accomplished by holding conversion results in programmable length registers for controllable time periods. A dual-channel ADC includes first and second delta-sigma modulators and a digital filter, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. An energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. The digital data subject to filter processing, is delayed by predetermined amounts. The dual-channel ADC is provided with a programmable channel delay mechanism. A differential delay equal to &Dgr;I-&Dgr;V is calibrated and compensated subject to an acceptable time delay for production of a correct energy value.

Abstract: A method and system of operating dynamic element matching (“DEM”) components of a DEM system with two or more power supplies are disclosed. A connection system of the DEM system is driven with one power supply operating at one voltage. Connection system couples to components that are to be matched and equalized in usage by ordering outputs to components and activating the components according to ordered outputs. A connection calculator of the DEM system is driven with another power supply operating at another voltage different from the one voltage. Connection calculator is coupled to the connection system, and connection calculator calculates an order of usage of components. A level shifter system level shifts voltage levels of signals from connection system to connection calculator, and another level shifter system level shifts voltage levels of signals from connection calculator to connection system.

Abstract: A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system filter includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value.

Abstract: A data conversion device is provided for storing digital data in a DAT (332) at a 16-bit word length and then recovering the data at a 24-bit word length with an overall reduction in truncation noise that would be inherently associated with data at the 16-bit word length. This is facilitated by noise shaping the data at the 16-bit word length prior to storage in the DAT (332) with a noise-shaping filter (324). This results in truncation noise in the lower portion of the frequency band being shifted to the higher portion of the band. When the data is recovered, it is converted to a 24-bit word length and then processed through a bandpass filter to filter out the higher frequency noise to yield a signal that has a maximum noise equal to or less than that in the lower portion of the band stored in the DAT (332). Since the truncation noise was shifted from the lower band to the upper band, this is a lower noise level than that inherently associated with the 16-bit word length.

Abstract: The present invention provides a bond tool utility software package which extracts bond pad location data from a semiconductor chip design stored in one of a number of known formats (e.g., Opus, GDSII, or the like) and extracts conductor location data from an AUTOCAD file of a chip frame design. The utility retrieves bonding connection data from a design ASCII file and generates a bonding diagram for the semiconductor assembly. The utility also contains a subroutine for applying bonding design criteria to the resultant bonding diagram to determine whether all bonds are within established guidelines. If an impermissible bond is formed, the user may be alerted that one or more bonding pads may have to be relocated. In one embodiment of the present invention, the bonding utility may interface with a semiconductor design circuit to generate a suggested fix to an impermissible bonding situation. One or more bonding pads may be moved in the semiconductor design to correct for potential bonding deficiencies.

Abstract: The present invention provides an apparatus and method for transmitting serial data bits in a computer system having both an IEEE 1394 bus and a universal serial bus. The arrangement comprises a networked entertainment system comprising a host computer system and a remote peripheral consumer electronics device. The host system includes a processor, a bus, a memory, and a graphics card. A host interface circuit is coupled to the host system to provide an interface with a remote peripheral device. A remote interface circuit is coupled to the remote peripheral device to provide an interface with the host system. The host interface circuit and the remote interface circuit are connected to each other by an IEEE 1394 bus cable. The host interface circuit provides a USB port for connecting a USB device to the host system. The remote interface circuit provides USB ports for connecting USB devices.

Abstract: A graphics subsystem includes hardware and/or software for permitting mip-maps to be dynamically switched based upon depth (Z) values. In addition, the system generates a SHIFT signal to permit automatic adjustment of texture parameters to facilitate retrieval of texture maps. The system includes a mip-map select logic or routine that compares the depth value of a pixel to be rendered with predetermined depth values. The depth values may be stored in a plurality of depth registers, and compared with the depth value of a pixel in a plurality of associated comparators. A mip-map is selected based upon the comparisons, and the SHIFT signal is generated to indicate the order of change with respect to a base reference mip-map. A texture engine receives the SHIFT signal and uses the associated base address of the selected mip-map and shifted texture parameters to define an address for the texture map.

Abstract: A graphics system includes a graphics controller for rendering polygons with texture using an improved MIP mapping technique. The graphics controller includes a polygon engine for rendering the pixels in a polygon and a texture map engine for selecting texture elements (“texels”) from an appropriate texture map to be applied to the pixels rendered by the polygon engine. The texture map engine generates texel coordinate values from pixel coordinate values provided by the polygon engine. The appropriate texture map is selected from a set of texture maps each varying from the others by the level of detail of the texture in each map. The graphics controller selects the appropriate level of detail texture map to use to increase speed, efficiency, and realism quality of the graphics system. The determination as to which level of detail texture map is appropriate is made by computing the area bounded by adjacent texel coordinates generated by the texture map engine.

Abstract: A portable radio telephone handset operates as a data transfer terminal as well as an analog cellular telephone subscriber station. Two modes of operation, an analog cellular communication mode and a Cellular Digital Packet Data (CDPD) mode, are available in the handset. The handset distinguishes between paging signals indicating CDPD mode communications and those indicating analog cellular communications. The handset also automatically preempts CDPD communications in favor of analog cellular communications such as those carried out in an AMPS configuration. The handset maintains an active status on a CDPD communication channel during a “sleep mode”, when the handset can carry out AMPS activity.

Abstract: A system and method is provided for providing optimal input and output impedances at a telecommunications interface. Input and output impedances can be adjusted manually, or the optimal impedance can be sensed and provided for automatically at the selected interface.

Abstract: A method and system for controlling a tuning voltage of a phase-locked loop circuit to an optimal value are disclosed. Minimum and maximum bias current values are defined for a bias current from the linear control loop circuit. The linear control loop circuit is coupled to the phase-locked loop circuit. The linear control loop circuit infinitely varies a current value for a current-controlled oscillator of the phase-locked loop circuit. The current value is based on a tuning current of the phase-locked loop circuit and the bias current. The bias current infinitely varies in value between the minimum bias current value and the maximum bias current value to direct the tuning voltage to an optimal value. The phase-locked loop circuit includes a phase detector, a filter, a voltage-to-current converter, a current adder, and the current-controlled oscillator coupled together in series.

Abstract: A novel multi-DSP system allows a main DSP to operate concurrently with an auxiliary DSP for implementing a filter algorithm. The main DSP and auxiliary DSP have separate program memories but share the same data memory. The auxiliary DSP program memory is mapped to the main DSP program memory to allow the main DSP to download filter process instructions from its program memory into the auxiliary DSP program memory. The auxiliary DSP fetches the instructions from its program memory to execute them. The auxiliary DSP is prevented from access to the shared data its program memory when this memory is occupied by the main DSP. An arbitration mechanism gives the auxiliary DSP access to the data memory only when the main DSP is not using this memory.

Abstract: A process and implementing computer system for graphics applications in which information files such as texture maps (TMs) are prioritized and stored in a local relatively fast RDRAM memory. The method of prioritization includes initially sorting the information files by order of the frequency with which corresponding graphics primitive elements are called by the application. The priority is adjusted such that the smaller TMs get an increase in their priority so that more TMs may be placed in faster graphics memory. Thereafter among similarly prioritized groups of information files, the larger of the files are first stored in the fast graphics memory and the remaining files are marked for storage in the system memory after the fast local memory has been fully utilized.

Abstract: A flat panel display controller is provided with a circuit for monitoring clocking signal(s) to the flat panel display. A clocking signal output to the flat panel display may be fed back to the display controller using a conventional I/O pad. In the preferred embodiment, the fed back clocking signal resets a counter. In a second embodiment, the fed back clocking signal may then pass through an edge detector whose output then resets the counter. The counter will overflow if a edge signal is not received within a predetermined time period. If an overflow occurs, the carry signal of the counter will initiate a flat panel power shutdown through power control circuitry. The clock signal for the counter may be derived from an off-chip oscillator such that if a failure occurs within the display controller, the counter will continue to function.

Abstract: A decimation filter has a low pass first stage of filtering in which multiple taps from a plurality of delay stages are summed together and then integrated to thereby provide suppression of high frequency noise in the input signal.

Abstract: Delay correction in a dual-channel analog-to-digital converter (ADC) is accomplished by insertion of coarse and fine delay correction registers prior to and after a frequency reduction element in a voltage channel. A dual-channel ADC includes first and second delta-sigma modulators and a digital filter, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. An energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. The digital data subject to filter processing is delayed by predetermined amounts. The dual-channel ADC is provided with a programmable channel delay adjustment in the voltage channel thereof. A delay differential equal to &Dgr;I−&Dgr;V is calibrated and compensated subject to an acceptable time delay for production of a correct energy value.

Abstract: A Digital Impairment Learning sequence which is designed for providing reliable estimate of digital impairments such as PAD, RBS, and CODEC type in the presence of analog impairments such as IMD, noise and changing line conditions. This estimate is used to derive optimum transmit symbol constellations for a modem connected digitally to a trunk so as to maximize its data transmission rate.

Abstract: The column surrounding an electron or ion beam is shielded with a second shield which is outside the column and isolated from the column, being connected to chassis ground at a location remote from the column. Also, wiring into the column is double shielded with the shields connected to ground at the end remote from the column and not at the column itself.

Abstract: Graphics software renders polygons with texture using an improved MIP mapping technique in which texels from multiple MIP maps are blended together. The software renders the pixels in a polygon and selects texture elements (“texels”) from an appropriate texture map to be applied to the pixels. The software further generates texel coordinate values to select texel values from a set of texture maps, each map varying from the others by the level of detail of the texture. The software then computes a scale factor for each texel value according an area bounded by adjacent texel coordinates. In one embodiment, vectors are defined for each the adjacent texels and the area is determined from the magnitude of the cross product of the vectors. The scale factor is then used to compute a weighted average of texels from one or more MIP maps. Further, for certain area values, no averaging occurs or, alternatively, the scale factor is set to 1.0.