Abstract: A mirrored data storage system utilizes a first host device and a local storage device for primary data storage and a second host device and a remote storage device for mirrored, fail-over storage on behalf of client devices. At periodic intervals (called checkpoints), the first host device initiates data synchronization between itself and the two storage devices and issues checkpoint information to ensure that each device maintains information for a common stable storage state. The local storage device synchronizes its stored data and forwards the checkpoint information to the remote storage device. The remote storage device maintains a copy (called a snapshot) of the data at the common stable storage state. Given the snapshot and the checkpoint information, the remote storage device can restore itself to the common stable storage state in the event of a failure of the first host device and/or the local storage device.

Abstract: A novel method and apparatus for encoding input data at a faster rate provides error detection, clock recovery, and reduction of spectral components near DC, and is capable of encoding data while embedding error detection information simultaneously. This encoding scheme may encode all input data in parallel while simultaneously embedding error detection information to quickly and properly encode input data.

Abstract: The present invention is directed to a system and method employing a dynamic logical identifier. In an aspect of the present invention, a method for accessing data utilizing an input/output interface may include providing an identifier for accessing a target device by a host and generating a logical identifier from the obtained identifier by the host. The logical identifier is transferred to an input/output interface and a look-up table is accessed utilizing the logical identifier by an input/output interface controller. The look-up table is included on the input/output interface, wherein the look-up table provides access between the input/output interface and the target device so as to enable the host to access the target device.

Abstract: A method for changing the internal timing of a memory to allow adjustment of the access time of the memory to be faster or slower by increasing or decreasing internal margins of the memory (bit line separation), respectively, utilizes the memory compiler for setting the number of core cells used for driving a self time column of the memory.

Abstract: The present invention is directed to a method and system for expanding volume capacity. A method of expanding volume capacity on a storage device may include receiving a request to expand capacity of a target volume by a requested amount. A first hierarchy is queried for unused capacity, wherein if unused capacity is at least one of greater than or equal to the requested amount, the unused capacity is positioned within the target volume. If unused capacity is less than the requested amount, at least one successive hierarchy is queried to locate unused capacity, which is at least one of greater than or equal to the requested amount, the successive hierarchy located at a logic block address further from a target volume logic block address than a first hierarchy logic block address. The unused capacity is then positioned to be included with the target volume.

Abstract: The present invention is directed to a system and method for reading and writing N-way mirrored storage devices. A method of reading data in a data storage system, where the data storage system may include a first data storage device, a second data storage device and a third data storage device, is provided. A first item of data is read from a first data storage device, a second item of data is read from a second data storage device, and a third item of data is read from a third storage device. The first item of data from the first storage device is compared with the second item of data from the second storage device and the third item of data from the third storage device. If the first item of data matches at least one of the second item of data and the third item of data, the first item of data is valid. If the first item of data does not match at least one of the second item of data and the third item of data, the second item of data is valid.

Abstract: A multipurpose configurable bus independent simulation bus functional model for testing a circuit is described. The multipurpose bus functional model utilizes a configurable data structure to interact with a device being tested by providing high-level test generation routines defined by the bus interface specified. The configurable data structure allows for verification of both signal timing and functional operation bus specifications. This data structure technique utilizes a standardized and parameterized method that allows variations and multiple instances of test bench models to be generated and instantiated in a design test environment. The bus functional model also sub-divides general functions and data structures into separate re-usable functional blocks. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other researcher to quickly ascertain the subject matter of the technical disclosure.

Abstract: In a storage environment or storage area network having multiple host devices and at least one storage array, the host devices access logical data volumes stored on the storage array through array controllers disposed in the storage array. Multiple host devices can request access to shared ones of the logical data volumes through multiple paths to multiple array controllers, but each logical data volume is controlled or owned by only one array controller at a time. Thus, ownership of shared logical data volumes is transferred between the array controllers as necessary on behalf of the requesting host devices. To prevent ownership transfers from occurring too often, however, ownership of the logical data volumes is made exclusive, or “sticky,” for a period of time after each transfer. During the exclusive ownership period of time, the ownership cannot be transferred.

Abstract: The invention is directed to novel promoters or mutants thereof from Chlorella virus DNA methyltansferase genes. A Chlorella virus gene promoter is operably linked to a first and/or second DNA sequence encoding a gene that is different from the Chlorella virus to form an expression cassette. An expression cassette can be introduced into prokaryotic and/or eukaryotic cells and can provide for a high level of expression of the gene encoded by the first and/or second DNA sequence. The invention also provides a method for screening other Chlorella virus genes for promoters that can function to express a heterologous gene in prokaryotic and/or eukaryotic hosts.

Abstract: A data storage system and a method of managing data in the storage system. A method of performing a write to a data storage system, including a first storage device and a second storage device, may include writing a first set of header information to a first storage device and a second storage device. The first set of header information includes a first sequence number and a second sequence number, in which the first set of header information includes a first sequence number incremented to indicate a change from the second sequence number. The method may also include returning status of completion of writing the second set of header information. Invalid data or an interruption may also be detected by examining the first and second sequence numbers. Data is written to the first storage device and the second storage device. Then, a second set of header information is written to a first storage device and a second storage device.

Abstract: The present invention is directed to a system and method of retaining peripheral ordering. A method for retaining peripheral ordering in an information handling system may include reading an ordered peripheral list (OPL) from a nonvolatile memory. A list of active peripherals attached to an I/O interface controller is obtained. An order of peripherals from the ordered peripheral list (OPL) is identified and assignments are assigned to the active peripherals attached to the I/O interface controller corresponding to the ordered peripheral list (OPL).

Abstract: A method and system for managing the transmission of data having variable priority over a transmission link are disclosed. Higher and lower priority data share a common transmission link such as a wireless communications network. Lower priority data such as a printing job does not interrupt or delay the transmission of higher priority data such as modem communications. When data to be transmitted is received by a transmitting device, a determination is made whether the data is higher or lower priority data. Higher priority data is transmitted, and lower priority data is saved in a memory for transmission during a lower priority time period. Errors occurring during the transmission of lower priority data are also saved for retransmission during a lower priority time period. A computer-based information handling system sends data to be transmitted to a transmitter for transmitting data over the transmission link. A receiver receives the data and sends the data to a remote device coupled to the receiver.

Abstract: The present invention is directed to a spanning tree method for K dimensional space. To address timing driven buffer insertion and clock routing problems clusters of points must be constructed in 3-dimensional space. The first and second dimensions are coordinates on a plane, while the third dimension is time which is arrival pin time for buffers insertion and clock latency for clock routing. In a first aspect of the present invention, a method includes partitioning an input set of points into a binary tree of partitions so that each leaf partition has maximally a defined number of points. Graph edges are made for the points by connecting each point to its closest points in every of 2K subspaces and the number of graph nodes is then reduced to a predefined value.

Abstract: The present invention is directed to a simple and scalable RAID XOR assist logic with overlapped operations. An apparatus suitable for performing overlapped operations may include an exclusive OR (XOR) unit suitable for performing an exclusive OR (XOR) operation. A memory communicatively coupled to the XOR unit, wherein the memory is suitable for storing a first item of data and a second item of data thereby enabling overlapped operations of the exclusive OR (XOR) unit.

Abstract: A system and method for controlling a plurality of parental control subsystems within an entertainment system is provided. The system includes a computer interfaced to a plurality of audio and/or audiovisual devices, wherein at least two of the audio and/or audiovisual devices within the system each comprise a native parental control subsystem or locking mechanism having adjustable parameters. A software locking mechanism operates the computer to allow a user to input one or more general parental control parameters and then sets the adjustable parameters of each native parental control subsystem within the system by mapping the parental control parameters onto each separate, native mechanisms for each device.

Abstract: A keyboard support apparatus comprises a storage compartment adapted to be mounted to the undersurface of an overhead cabinet, a low ceiling, and the like. The keyboard support apparatus further comprises at least one extendable support arm pivotally coupled at one end to the storage compartment, and a keyboard platform pivotally coupled at opposite sides to the other end of the support arms. Each support arm is adapted to extend downwardly from the storage compartment to position the keyboard platform below the storage compartment in an operational configuration. Each support arm is also adapted to contract upwardly to position the keyboard platform inside the storage compartment in a storage configuration.

Abstract: A battery release mechanism for releasably securing a battery to a power tool is disclosed. The battery release mechanism includes a battery receiving portion integral with a handle portion of the power tool and an attachment portion integral with the battery. The attachment portion is configured to engage the battery receiving portion. The battery release mechanism also includes a closure member that is operable with and transversely disposed within the battery receiving portion. The closure member is configured to secure the battery within the battery receiving portion when the closure member is in a “lock” position. The closure member has a first end and a second end opposite the first end. The first end is disposed through a side wall of the tool housing and defines a push button for selectively moving the closure member from the “lock” position to a “release” position.

Abstract: A manifold assembly is provided for controlling and distributing compressed air from an air compressor to one or more air powered tools. The manifold assembly may be attached directly to the air compressor, or, alternately, removed from the air compressor and coupled thereto via an air conduit, e.g., an air hose or the like, so that the manifold assembly can be used at locations remote from the air compressor.

Abstract: A clock tree uses a temporary clock buffer or reference signal in a clock tree deskew circuit to dynamically minimize skew in a variable delay clock signal that synchronizes operation of synchronized circuit components of an integrated circuit. Skew between the temporary clock buffer signals are minimized by providing identical path lengths and path geometries. The clock tree deskew circuit reduces the clock tree skew in repeated intervals over a period of time. When the tree deskew circuit is deskewed for a multilevel clock tree, the temporary clock net of that level of the clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew. The clock tree deskew circuit adjusts the variable delay clock buffer signal of each pair toward the temporary clock buffer signal of the pair to reduce the skew between the two clock buffer signals.

Abstract: The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets. For example, an interscalable interconnect maybe provided that is scalable and isochronous capable. Additionally, an abstract language may be provided to be able to describe interconnecting core functions. Further, a self-programmable chip may be provided that, upon receiving a construct, it could program itself to achieve the desired functionality, such as through the use of on-chip knowledge and the like.