Abstract: The present invention is directed to an advanced storage controller that is capable of providing parallel processing capabilities to a host processing system connected storage system to increase performance, functionality and reliability of the entire computing system. The advanced storage controller comprises at least one input interface and at least one output interface, a host device simulation component, a cache device component, a physical device component and a management component. Such an advanced storage controller further, includes one or more processor elements and storage elements, which may be shared by the components or dedicated to one component. Additionally, the advanced storage controller is scalable by the static or dynamic addition of components, processors and/or memory.

Abstract: The present invention is directed to a method and apparatus of IC implementation based on a C++ language description. In an exemplary aspect of the present invention, a method for evaluating a C++ description by an IC includes the following steps. First, a C++ description including a C++ program is provided. Then, the C++ program is stored in a first memory module (e.g., a ROM, or the like) of an IC. Next, a scalar input and/or an input array may be provided to the IC. Then, the C++ program may be executed by a control device module of the IC. Next, a scalar output and/or an output array may be read from the IC.

Abstract: A method for providing online raid migration without non-volatile memory employs reconstruction of the RAID drives. In this manner, the method of the present invention protects online migration of data from power failure with little or no performance loss so that data can be recovered if power fails while migration is in progress, and migration may be resumed without the use of non-volatile memory.

Abstract: A search engine apparatus having a built-in functional test may include an input generator, a search engine, a pseudo search engine and a comparator. The inputs generator is suitable for generating outputs including commands and points associated with the commands. The search engine and the pseudo search engine are communicatively coupled to the inputs generator. The search engine suitable for performing search and edit operations and the pseudo search engine is suitable for simulating the search engine by generating pseudo search engine outputs. The comparator is communicatively coupled to the search engine and the pseudo search engine, and is suitable for comparing outputs received from the search engine and pseudo search engine.

Abstract: The present invention is directed to a method and system for providing, a host input/output (I/O) module, a controller and application specific integrated circuit (ASIC) for utilization in transparent switched fabric data storage transport. The system implements I/O modules capable of translating between communication protocols for providing common message passing multi-channel data transport for data storage while providing apparent I/O circuit exclusivity to controllers. Implementing the system of the present invention allows for a common data transport system permitting component scalability and virtualization.

Abstract: The present invention is directed to a system and method of cache management for storage controllers. In an aspect of the present invention, a system for storing electronic data may include a host and a data storage apparatus communicatively coupled to the host. The host has cache coherency functionality. The data storage apparatus includes a first storage controller communicatively coupled to at least one storage device, the first storage controller further coupled to a first cache. A second storage controller is also included, which is communicatively coupled to at least one storage device, the second storage controller further coupled to a second cache. The cache coherency functionality of the host provides coherency of the first cache coupled to the first storage controller with the second cache coupled to the second storage controller.

Abstract: A system, method and apparatus for providing and utilizing a storage cache descriptor by a storage controller are disclosed which provide the ability to effectively balance the size of storage controller cache blocks and the amount of data transferred in anticipation of requests, such as requests by a host. The apparatus may include a storage device, a storage controller and a cache. The storage controller stores electronic data in the cache by including a cache descriptor that defines data contained in a cache block, the cache descriptor including at least one field describing a device block of the cache block. The at least one field may include, by way of example, at least one of a present field, modified field, pinned field and write-in progress field.

Abstract: The present invention is directed to a train detection system for detecting the velocity, presence, and direction of a railroad car which may be utilized in existing railroad crossing installations. The train detection system is suitable for self-testing of its components and if an anomaly has been detected, the train detection system is capable of placing the system in a fail-safe state. The train detection system of the present invention is also capable of constant communication between the sensor of said system and the implementing device of the train detection system via a wireless link.

Abstract: The present invention is directed to an apparatus for providing convenient control of a power tool electrical system. A switch assembly of the present invention includes a first actuator and a second actuator, which is disposed remotely from the switch and first actuator. The second actuator is connected via a coupling device, such that user manipulation of either the first or second actuator is capable of controlling electricity flowing to the motor. Including a second actuator may permit the user to retain greater control over the tool when turning the power on or off. In additional exemplary aspects, a coupling device included in the switch assembly is configured and arranged so as to prevent inadvertent damage to the power tool such as by accidental engagement of a shaft lock while the motor is operating.

Abstract: The present invention is an apparatus and system for providing a high quality spiral inductor in an integrated circuit environment. A layer of inductor may be placed within the metal layers along with negative capacitance generation circuitry of the present invention to compensate for the capacitance associated with the metal layers adjacent to the inductor to provide a higher quality factor for the inductor. Advantageously, circuitry of the present invention may be employed within an integrated circuit without modifying the layer structure of the integrated circuit. Additionally, values of the components of the circuitry may be selectively and independently chosen to synthesize a variable range of negative capacitance.

Abstract: A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a read enable signal, a write enable signal, and a reset signal as inputs. Advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. Delay circuitry may be added such that the generated clock signal has sufficient fan out and is sufficiently stable.

Abstract: The present invention is directed to a method for generating a tech-library for a logic function. A logic function has many representations. For each representation, a circuit for realizing the representation is decomposed into a combination of instances. An instance is a component logic circuit of a general logic circuit. There are pre-created tech-libraries for the instances. For example, a pre-created tech-library is created by categorizing tech-descriptions for primitive physical circuits based on a negation index. Thus, tech-descriptions for a circuit for realizing a representation are calculated from a combination of elements of the pre-created tech-libraries. Each calculated tech-description is compared with each existing element of a tech-library for the logic function. When a calculated tech-description has at least one marked parameter better or smaller than that of all existing elements of the tech-library for the logic function, the calculated tech-description is added to the tech-library.

Abstract: A microprocessor based system automatically detects the occurrence of certain conditions in the microprocessor. The conditions may include a determination of data corruption in the microprocessor. If a determination is made that data is corrupted, the microprocessor may be reloaded from a non-volatile memory. During a reload, a microcontroller controls the microprocessor. The non-volatile memory may be a flash memory or non-volatile random access memory.

Abstract: An apparatus and method for dynamically enabling and disabling interrupt coalescing in a data processing system. The present invention involves consistently monitoring IO load on an IOP of an IO adapter. The firmware on the IO adapter may have a global variable that stores counters for PCI function registers. Each counter tracks the number of outstanding IOs of a corresponding PCI function register. The counter is incremented whenever a new IO is received and is decremented upon posting the completed message back to the OS. A timer interrupt is generated periodically so that an ISR may be periodically performed. In the ISR, the maximum value stored of each counter seen since last timer interrupt is analyzed. When the maximum value stored is greater than a predetermined threshold value, the interrupt coalescing is enabled.

Abstract: The present invention is directed to a system and method for providing a data backup to an information handling system using software updates. The information handling system has one or more applications included thereon and is capable of being communicatively coupled to a remote server through a network connection. A data package is created based upon configuration data and application data stored on the server. The configuration data includes data previously obtained from the information handling system, such as settings and user data. The application data includes data corresponding to the applications included on the information handling system. The data package is formatted into a software update format and transmitted over the network connection to the information handling system. The data package is suitable for restoring the information handling system after failure, and may be utilized by the information handling system as a software update to restore itself.

Abstract: A reconfigurable memory controller includes a plurality of communicatively coupled memory controllers. The plurality of memory controllers may be configured into a first configuration based on a grouping of memory controllers and then reconfigured into a second configuration based on a different grouping of memory controllers, where the first and second configurations have different performance bandwidths for accessing memory.

Abstract: A system is provided for channeling high frequency signals through sheet metal containment within an electronic device. In exemplary embodiments of the invention, an electronic device employing the system includes a midplane circuit board. One or more interface modules may be coupled to the midplane circuit board, for example, for providing a high frequency interconnect with other devices such as Fiber Channel or the like. A midplane chassis shield is disposed within the device's housing adjacent to the midplane circuit board so that the interface modules interconnect with the midplane circuit board through apertures formed in the shield wherein the midplane circuit board, midplane chassis shield and interface module cooperate for providing a low impedance tunnel for channeling high frequency signals to ground.

Abstract: The method and circuit of the present invention compensates a timing change over PVT variations without adverse impact on the system. The method and circuit uses two digital programmable delay circuits which have a Master/Slave relationship. The master programmable delay circuit tracks a delay over PVT and readjusts the delay whenever there is a need for calibration due to PVT variations. The slave programmable delay circuit compensates the timing change by delaying the real clock signal when the master programmable delay circuit completes the delay locking process. The resulting circuit is small, flexible, PVT calibrated, and consumes very little power. It can be used with any reference clock to support various timing requirements at different frequencies.

Abstract: A downdraft table includes an enclosure connected to a downdraft mat member that provides a work surface, a support apparatus, and a conduit member capable of providing dust collection to the work surface. The downdraft mat includes a plurality of through points and is disposed upon a top surface of the enclosure. The conduit member includes one or more connection portals enabling a vacuum device to be connected to the conduit member and provide dust collection to the work surface.

Abstract: The present invention is directed to fast flexible search and edit pipeline separation. A system suitable for providing a search may include a central controller and at least one search engine. The central controller is suitable for implementing search and edit operations. The at least one search engine is communicatively coupled to the central controller. The central controller performs parallel execution of a search operation and an edit operation through utilization of the at least one search engine.