Patents Represented by Attorney Suiter West Swantz PC LLO
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Method and apparatus for finding optimal unification substitution for formulas in technology library
Patent number: 7003739Abstract: The present invention is directed to a method and apparatus to find an optimal unification substitution for formulas in a technology library. In an exemplary aspect of the present invention, a method for finding an optimal unification substitution for formulas in a technology library during integrated circuit design may include the following steps: (a) receiving input including a list L of pairs of formulas in standard form, a set S of substitutions for variables, a right part e(x1, . . . , xp) of an identity, and an information I={t, h, r, a, p} on best application; (b) when the list L is not empty, extracting and removing first pair (ƒ?(A?1, . . . , A?n?), g?(B?1, . . . , B?m?)) from the list L; (c) removing head inverters and buffers from formulas ƒ?(A?1, . . . , A?n?) and g?(B?1, . . . , B?m?)) and obtaining a pair (ƒ(A1, . . . , An), g(B1, . . . , Bm)); (d) when the ƒ is a commutative operation but neither a variable nor constant, and when heads of the formulas ƒ(A1, . . . , An) and g(B1, . . .Type: GrantFiled: November 21, 2003Date of Patent: February 21, 2006Assignee: LSI Logic CorporationInventors: Elyar E. Gasanov, Alexander S. Podkolzin, Alexei V. Galatenko -
Patent number: 6999975Abstract: A method and system for identifying records with a valid address, but invalid name information automatically determines if an address is in a set (file) of known valid addresses, and that the name is not in the subset of names associated with the address by calculating the acceptable probability of a match between the addresses and names. In order to calculate the acceptable probability of a match heuristics may be determined for various operating systems, applications, application environments, etc. Integration of the method and system of present invention may be determined by a particular condition, configuration, and/or environment at any given period of time and may, for example, be incorporated in environments such as a computer controlled printer (Inkjet, Laser, etc.) environment or database ETL (Extract, Transform and Load) environment.Type: GrantFiled: January 22, 2002Date of Patent: February 14, 2006Assignee: Cas, Inc.Inventor: Michael E. Garrean
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Patent number: 7000092Abstract: The present invention is directed to a system and method for heterogeneous multiprocessor reference design. In an aspect of the present invention, a method of designing a multiprocessor integrated circuit may include receiving a specification for an integrated circuit having multiprocessors, the specification having a desired functionality. Functional components are chosen which provide the desired functionality of the received specification. The functional components are implemented in a modular multiprocessor reference design as an example system for the multiprocessor integrated circuit. The implemented functional components of the modular multiprocessor reference design may be suitable for testing software for operation by the multiprocessor integrated circuit. Moreover, the modular multiprocessor reference design enables testing of interaction of functional components for providing the desired functionality of the received specification.Type: GrantFiled: December 12, 2002Date of Patent: February 14, 2006Assignee: LSI Logic CorporationInventors: Judy Gehman, Jeffrey Holm, Steven Emerson
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Patent number: 6995966Abstract: A method and apparatus for fire prevention in electronic equipment utilizes infrared imaging technology to monitor a substantial region of an enclosure within the electronic equipment. For example, a shelf within a computer cabinet may have a lens and thermal sensor array placed within to detect changes in temperature. A processor interprets the data from the thermal sensor array to determine whether to send an alert to an operator and/or to shut down a power supply.Type: GrantFiled: December 9, 2002Date of Patent: February 7, 2006Assignee: Network Appliance, Inc.Inventors: Zoltan Zansky, Joseph Tupy
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Patent number: 6996629Abstract: The present invention is directed to a system and method of providing an embedded input/output interface failover. An apparatus for providing an input/output interface with failover functionality between a host and a target may include a first data transfer route suitable for communicatively coupling the apparatus to a host system, a second data transfer route suitable for communicatively coupling the apparatus to a target, and a third data transfer route suitable for communicatively coupling the apparatus to the target. A memory suitable for storing electronic data is also included, the memory including a program of instructions. A controller is communicatively coupled to the first data transfer route, the second data transfer route, the third data transfer route and the memory.Type: GrantFiled: October 31, 2001Date of Patent: February 7, 2006Assignee: LSI Logic CorporationInventor: Louis Odenwald
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Patent number: 6993677Abstract: The present invention is directed to a system and method for data verification in a RAID system. A method of verifying data in a RAID system may include reading a first item of data from a first data storage device and a second item of data from a second data storage device. The first item of data from the first storage device is compared with the second item of data from the second storage device. If the first item of data does not match the second item of data, a third item of data is read from a third data storage device. The third item of data is compared with the first item of data and the second item of data.Type: GrantFiled: June 14, 2001Date of Patent: January 31, 2006Assignee: LSI Logic CorporationInventor: Alden R. Wilner
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Patent number: 6988260Abstract: The present invention is directed to a method and apparatus for optimizing fragmentation of integrated circuit boundaries for optical proximity correction (OPC) purposes. The present invention may balance the number of vertices and the “flexibility” of the boundary and may recover fragmentation according to the process intensity profile along the ideal edge position to obtain the best decision for OPC.Type: GrantFiled: December 18, 2003Date of Patent: January 17, 2006Assignee: LSI Logic CorporationInventors: Stanislav V. Aleshin, Marina M. Medvedeva, Sergei B. Rodin, Eugeni E. Egorov
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Patent number: 6986369Abstract: The present invention is directed to a router depth adjustment mechanism for minimizing rapid course depth adjustment for standard and plunge routers. Routers with rapid or course adjustment mechanisms may permit a router motor housing to drop suddenly, if the user in inattentive. Sudden adjustments may result in damage to the router and even user injury. The mechanism of the present invention includes a threaded shaft and a biased thread engaging member which may be disengaged for rapid adjustment. A restraining device and/or a break may be included to minimize the rate of change.Type: GrantFiled: November 12, 2002Date of Patent: January 17, 2006Assignee: Porter-Cable CorporationInventors: Randy G. Cooper, Greg K. Griffin, Derrick Kilbourne, Mark A. Etter, Ginger L. Allen
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Patent number: 6980149Abstract: A mood response system enables a user to communicate audio messages to another, which correspond with the emotional state of the user, over a speaker. The mood response system comprises a handheld controller disposed with a keypad, a message set switch, and three message sets, each comprising up to ten individual audio messages, which may be played over the speaker. The mood response system further includes the capability to record audio messages from the user, store them in one of the message sets, and play the recorded audio messages over the speaker.Type: GrantFiled: October 31, 2002Date of Patent: December 27, 2005Inventor: Dennis Meyer
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Patent number: 6977833Abstract: An embedded memory on an integrated circuit chip is capable of being isolated from other on chip and off chip circuitry during power failure modes on the integrated circuit chip. The embedded memory preferably has its own external power supply. When power on chip fails or falls below a threshold level, input to and output from the embedded memory is prohibited by CMOS isolation cells. The CMOS isolation cells are controlled by enable signals and the power level of other power supplies within the integrated circuit.Type: GrantFiled: October 28, 2003Date of Patent: December 20, 2005Assignee: LSI Logic CorporationInventors: Brian A. Day, Frantisek Gasparik
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Patent number: 6973407Abstract: The present invention provides a method for capturing data suitable for creating a Serial ATA eye diagram. A Serial ATA host controller including a first and a second Serial ATA ports is powered up, where receive lines of the first Serial ATA port are short-circuited to receive lines of the second Serial ATA port, and the first Serial ATA port is communicatively coupled to a Serial ATA drive. An initialization pattern from the Serial ATA drive is received by the first and the second Serial ATA ports. An ALIGN/SYNC pattern is transmitted over transmit lines of the second Serial ATA port. Data transmitted over the transmit lines of the second Serial ATA port is captured using a high impedance differential probe and an oscilloscope. The captured data may be used to create a Serial ATA eye diagram for the second Serial ATA port on the oscilloscope.Type: GrantFiled: May 13, 2004Date of Patent: December 6, 2005Assignee: LSI Logic CorporationInventor: Moby Abraham
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Patent number: 6966085Abstract: A sleep system, for providing a bed, includes a frame with cross support members coupled with a first and second panel assembly. A sleep support mechanism operationally engages the first and second panel assemblies with one another and further engages a pad to provide adjusting support to the user. The sleep support mechanism employs a cone coupled with a first and second spring, the first and second spring further coupling with the first and second panel assemblies, and the cone engaging with the pad to provide the adjustable support capability.Type: GrantFiled: March 11, 2004Date of Patent: November 22, 2005Inventors: W. Gene Cretsinger, Steven R. Kunert
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Patent number: 6966032Abstract: An audio assisted setup apparatus and method include providing a set of audio instructions stored in a memory, and presented to a computer purchaser to assist in setup of a computer system. The apparatus is activated automatically upon a triggering event, and runs before the computer is set up.Type: GrantFiled: September 30, 1999Date of Patent: November 15, 2005Assignee: Gateway Inc.Inventor: Glen J. Anderson
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Patent number: 6948139Abstract: A method for combining states of a state machine employs manipulation of case statements in the RTL code implementing the state machine to allow selectable state combinations without duplication of code so that errors inherent in maintaining duplicate copies of the same RTL code may be eliminated.Type: GrantFiled: December 19, 2002Date of Patent: September 20, 2005Assignee: LSI Logic CorporationInventor: Richard L. Solomon
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Patent number: 6947287Abstract: A universal modular power supply carrier mounts different sized power supplies within a substantially rectangular body designed for thermal and electromagnetic emissions control. The power supplies are preferably secured within the carrier body. Input connectors may be alternating current or direct current. The output connector may be pin, or blade, and socket with blind mating capability. One or more direct current voltages may be output by the carrier to a motherboard or other electronic circuitry. The universal modular power supply carrier may be contained in a one-size universal electronic equipment cabinet.Type: GrantFiled: December 16, 2002Date of Patent: September 20, 2005Assignee: Network Appliance, Inc.Inventors: Zoltan Zansky, James Robert Davis
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Patent number: 6943633Abstract: A ring oscillator that uses active negative capacitance at one or more stages of the ring oscillator to adjust the frequency of oscillation. By using a negative capacitance generator, negative capacitance may be placed in shunt with each stage of the ring, thereby reducing the effective input capacitance. Tuning of the ring oscillation frequency is accomplished without changing the bias point of each stage. The ring oscillation frequency may be increased, rather than reduced as in current approaches.Type: GrantFiled: September 2, 2003Date of Patent: September 13, 2005Assignee: LSI Logic CorporationInventor: Prashant Singh
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Patent number: 6938809Abstract: A nail lockout assembly provides a way for an operator of a nail gun to have determined whether the nails being employed are properly aligned to allow for efficient operation of the nail gun. The nail lockout assembly may be employed in a nail loading assembly, such as an adjustable angle magazine, which is coupled with a nail driving assembly. A slotted guide member disposed in a housing of the nail loading assembly provides a determination of the angle of the nail loading assembly relative to the nail driving assembly through operational engagement with a projection. A linkage bar is coupled with the slotted guide member and translates the angle of the nail loading assembly to a pusher which engages a nail loaded in the nail loading assembly. A cover serrated member is coupled with a cover of the nail loading assembly. A pawl assembly is coupled with the linkage bar and may engage with the cover serrated member. An adapter couples with the pusher and the pawl assembly enabling rotational movement in each.Type: GrantFiled: September 17, 2003Date of Patent: September 6, 2005Assignee: Porter-Cable CorporationInventor: John W. Schnell
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Patent number: 6941408Abstract: The present invention is directed to an interface. In an aspect of the present invention, an interface system suitable for coupling a bus interface controller with a back-end device includes a bus interface controller and a back-end device in which the back-end device is coupled to the bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data. The data transfer interface includes an inbound data transfer interface suitable for transferring data and an outbound data transfer interface suitable for transferring data. The inbound data transfer interface and the outbound data transfer interface are suitable for processing commands simultaneously.Type: GrantFiled: September 30, 2002Date of Patent: September 6, 2005Assignee: LSI Logic CorporationInventor: Richard L. Solomon
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Patent number: D511429Type: GrantFiled: October 15, 2004Date of Patent: November 15, 2005Inventor: Tou Lor
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Patent number: D515105Type: GrantFiled: December 28, 2004Date of Patent: February 14, 2006Assignee: Shandong Foton Heavy Industries, Co., Ltd.Inventors: Jinfu Wang, Zhi Chi, Jinguang Zhu, Minge Chen, Jinhua Wang, Wenzhong Liu, Yuanfu Wang, Zhengyu Li