Abstract: A microprocessor based system automatically detects the occurrence of certain conditions in the microprocessor. The conditions may include a determination of data corruption in the microprocessor. If a determination is made that data is corrupted, the microprocessor may be reloaded from a non-volatile memory. During a reload, a microcontroller controls the microprocessor. The non-volatile memory may be a flash memory or non-volatile random access memory.
Type:
Grant
Filed:
August 27, 2002
Date of Patent:
June 6, 2006
Assignee:
LSI Logic Corporation
Inventors:
Stephen Piper, Matthew Trembley, Dennis Craton
Abstract: An apparatus and method for dynamically enabling and disabling interrupt coalescing in a data processing system. The present invention involves consistently monitoring IO load on an IOP of an IO adapter. The firmware on the IO adapter may have a global variable that stores counters for PCI function registers. Each counter tracks the number of outstanding IOs of a corresponding PCI function register. The counter is incremented whenever a new IO is received and is decremented upon posting the completed message back to the OS. A timer interrupt is generated periodically so that an ISR may be periodically performed. In the ISR, the maximum value stored of each counter seen since last timer interrupt is analyzed. When the maximum value stored is greater than a predetermined threshold value, the interrupt coalescing is enabled.
Type:
Grant
Filed:
December 13, 2002
Date of Patent:
May 30, 2006
Assignee:
LSI Logic Corporation
Inventors:
Owen N. Parry, Brad D. Besmer, Stephen B. Johnson
Abstract: A method for validating operation of a fiber link when the fiber link is initialized includes the steps of entering a trial link up state upon receiving a command to initialize the fiber link so that normal commands to other devices within the fiber channel loop are not resumed, and thereafter entering a final link up state and resuming normal commands to other devices within the fiber channel loop. In exemplary embodiments, the method may be implemented by devices within a system such as a disk array system of a storage area network (SAN), or the like.
Abstract: The present invention is directed to a method and apparatus for mapping platform-based design to multiple foundry processes. According to an exemplary aspect of the present invention, a predefined (or pre-specified) slice is successfully mapped on to a first fabrication process with a first set of design rules to produce a first result. Then the slice's ability to be mapped to a second fabrication process with a second set of design rules is evaluated to produce a second result. Next, the comparison between the two results is computed to produce a third result. The third result may be then used to modify the slice architecture, optimize the metalization process and/or modify the first or second fabrication process. The slice definition, the first set of design rules, the second set of design rules, the first result, the second result, and the third result may be stored into a database.
Abstract: The present invention is directed to a system and method for providing a data backup to an information handling system using software updates. The information handling system has one or more applications included thereon and is capable of being communicatively coupled to a remote server through a network connection. A data package is created based upon configuration data and application data stored on the server. The configuration data includes data previously obtained from the information handling system, such as settings and user data. The application data includes data corresponding to the applications included on the information handling system. The data package is formatted into a software update format and transmitted over the network connection to the information handling system. The data package is suitable for restoring the information handling system after failure, and may be utilized by the information handling system as a software update to restore itself.
Abstract: A method and circuit allows flexible control for termination of a signal line. The mode of operation of the circuit may be set manually or automatically. A software controller provides software control of the signal line. A bus terminator is tied to the signal line. A feedback line from the bus terminator permits monitoring the logic level on the signal line by the software controller. The modes permit software control of the termination or operator setting of the termination by grounding of the signal line or pulling up the signal line to the power line.
Type:
Grant
Filed:
December 8, 2003
Date of Patent:
May 16, 2006
Assignee:
LSI Logic Corporation
Inventors:
Justin McCollum, Stephen Piper, Dennis Craton
Abstract: A reconfigurable memory controller includes a plurality of communicatively coupled memory controllers. The plurality of memory controllers may be configured into a first configuration based on a grouping of memory controllers and then reconfigured into a second configuration based on a different grouping of memory controllers, where the first and second configurations have different performance bandwidths for accessing memory.
Type:
Grant
Filed:
December 11, 2002
Date of Patent:
May 9, 2006
Assignee:
LSI Logic Corporation
Inventors:
Gary P. McClannahan, Gary S. Delp, George W. Nation
Abstract: The method and circuit of the present invention compensates a timing change over PVT variations without adverse impact on the system. The method and circuit uses two digital programmable delay circuits which have a Master/Slave relationship. The master programmable delay circuit tracks a delay over PVT and readjusts the delay whenever there is a need for calibration due to PVT variations. The slave programmable delay circuit compensates the timing change by delaying the real clock signal when the master programmable delay circuit completes the delay locking process. The resulting circuit is small, flexible, PVT calibrated, and consumes very little power. It can be used with any reference clock to support various timing requirements at different frequencies.
Abstract: A system is provided for channeling high frequency signals through sheet metal containment within an electronic device. In exemplary embodiments of the invention, an electronic device employing the system includes a midplane circuit board. One or more interface modules may be coupled to the midplane circuit board, for example, for providing a high frequency interconnect with other devices such as Fiber Channel or the like. A midplane chassis shield is disposed within the device's housing adjacent to the midplane circuit board so that the interface modules interconnect with the midplane circuit board through apertures formed in the shield wherein the midplane circuit board, midplane chassis shield and interface module cooperate for providing a low impedance tunnel for channeling high frequency signals to ground.
Abstract: A downdraft table includes an enclosure connected to a downdraft mat member that provides a work surface, a support apparatus, and a conduit member capable of providing dust collection to the work surface. The downdraft mat includes a plurality of through points and is disposed upon a top surface of the enclosure. The conduit member includes one or more connection portals enabling a vacuum device to be connected to the conduit member and provide dust collection to the work surface.
Abstract: An apparatus and method for enhancing data availability by implementing inter-storage-unit communication in a data processing system. A Remote Volume Mirroring (RVM) system may be leveraged according to the present invention to provide volume failover by enhancing the functionality of the arrays, in a manner transparent to a host.
Abstract: The present invention is directed to a method and apparatus for making mask edge corrections using a gradient method for high density chip designs. The present invention uses a newly defined cost function.
Type:
Grant
Filed:
December 18, 2003
Date of Patent:
May 2, 2006
Assignee:
LSI Logic Corporation
Inventors:
Marina M. Medvedeva, Stanislav V. Aleshin, Eugeni E. Egorov, Sergei B. Rodin
Abstract: The present invention is a method and system for supplementing power when a power supply has a power failure. An amount of inrush current produced upon resumption of input power is reduced. Supplemental power circuitry may include a rechargeable battery that may supply power during a power failure without generating a large inrush current when input power is regained. The period of time supplemental power may be provided is also increased.
Abstract: The present invention is directed to fast flexible search and edit pipeline separation. A system suitable for providing a search may include a central controller and at least one search engine. The central controller is suitable for implementing search and edit operations. The at least one search engine is communicatively coupled to the central controller. The central controller performs parallel execution of a search operation and an edit operation through utilization of the at least one search engine.
Abstract: A nail checker assembly, disposed with a nail loading assembly, provides a pivoting probe assembly which engages with a nail, advancing down the nail loading assembly, and determines if the nail is correctly aligned. If the nail is properly aligned the pivoting probe assembly, coupled with a pivoting probe base assembly, rotates and allows the nail to advance. If the nail is improperly aligned the pivoting probe assembly engages with a lock ledge assembly providing a stop and hindering the advancement of the nail.
Abstract: The present invention is directed to a system and method for classification of media content based upon user-defined classifications. A compilation of media content in conformity with the user-defined classifications and desired criteria may be automatically produced in accordance with the present invention. The system and method of the present invention may also be capable of selecting pieces of media content depending upon the user's mood and current activity.
Abstract: The present invention is a method and system for associating metadata with user data in a storage array in a manner that provides independence between metadata management and a storage controller's cache block size. Metadata may be associated with user data according to multiple fashions in order to provide a desired performance benefit. In one example, the metadata may be associated according to a segment basis to maximize random I/O performance and may be associated according to a stripe basis to maximize sequential I/O performance.
Abstract: The present invention is directed to a suitcase style air compressor assembly having an extensible handle bar assembly, a wheel assembly, and a integral storage container. When the extensible handle bar assembly is fully extended, the suitcase style air compressor assembly may be transported by utilizing the extensible handle bar assembly and the wheel assembly. When the suitcase style air compressor assembly reaches a worksite, the extensible handle bar assembly may be retracted so that the suitcase style air compressor assembly does not occupy a large space. The air compressor includes a storage container for storing air hoses, power cords, tools, and the like.
Type:
Grant
Filed:
November 5, 2004
Date of Patent:
April 11, 2006
Assignee:
Black & Decker Inc.
Inventors:
John W. Hardin, Gary Krentzer, Travis Patterson, Mark W. Wood, Steve A. Jordan, James Vintzel, J. Cody Stilwell, Gary D. White, Stephen J. Vos
Abstract: The present invention is directed to a method and apparatus of automatic power management control for Serial ATA interface. In an exemplary aspect of the present invention, an idle or active condition of Serial ATA interface is automatically detected. When Serial ATA is in an idle condition, idle time of Serial ATA interface is counted using a power down counter whose frequency is determined by a programmable register based on input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state. When a power down counter value is equal to a second value, a request for a Slumber power state is asserted, and Serial ATA interface is put into a Slumber power state.
Type:
Grant
Filed:
June 25, 2003
Date of Patent:
April 11, 2006
Assignee:
LSI Logic Corporation
Inventors:
Vetrivel Ayyavu, Brian Day, Ganesan Viswanathan