Abstract: The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. Using the circuit of the invention data is transferred in response to an internal write signal. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.

Abstract: The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.

Abstract: A capacitor and method for forming the capacitor having HSG polysilicon with reduced dielectric bridging, increased capacitance, and minimal depletion effects. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is deposited at a temperature adjusted to cause a nucleation of the second polysilicon layer. As a result of the nucleation the second polysilicon layer is altered to resemble hemispherical grains. Next the first and second polysilicon layers are oxidized in an oxygen/phosphine ambient. During the oxidation portions of the first and second polysilicon layers are consumed forming a phosphine rich oxide layer on the surface of the hemispherical grains and in portions of the first polysilicon layer lying between the grains which are reduced in size due to the oxidation. A wet etch is then performed to remove the oxide layer. Phosphorous ions are driven into the hemispherical grains during the oxidation thereby doping the grains.

Abstract: Silicon is employed as a reducing agent in an acid bath to adsorb noble metals present as contaminants in the acid. In the manufacture of silicon devices for electronic memory and other devices, polonium-210 is adsorbed by silicon getters to reduce soft error rate attributable to alpha particle emissions from the radioactive polonium. The noble metals in addition to polonium which can be plated onto silicon using the disclosed method are gold, silver, platinum, copper, palladium, mercury, selenium and bismuth.

Abstract: A method for depositing tungsten nitride uses a source gas mixture having a silicon based gas, such as silane for depositing the tungsten nitride to overlie a deposition substrate. A non-planar storage capacitor has a tungsten nitride capacitor electrode.

Abstract: The invention is a process for cleaning a chamber after a chemical vapor deposition has been performed therein. A residue formed during the deposition is combined with a reactive species to form a gas containing an organic substance once found in the residue and to form a film on the chamber walls and internal parts. The gas and the film are removed from the chamber. The formation of a polymer byproduct on the chamber walls and other internal parts of the chamber is minimized by the method of the invention.

Abstract: The invention is a circuit and a method for resetting a wordline by driving a potential of the wordline toward a ground reference potential prior to driving the potential of the wordline to a negative potential.

Abstract: A socket having primary conductors and secondary conductors. The socket provides electrical connection between active circuitry installed on a substrate and external circuitry. The impedance between each primary conductor and each secondary conductor is a predetermined value selected in order to match impedances of the active circuitry and the external circuitry.

Abstract: An inductively coupled plasma chamber having a capacitor electrode during cleaning of the plasma chamber.

Abstract: A video RAM having isolated array sections for providing write function that will not affect other array sections. The whole VRAM memory array does not have to be completely read before writing new pixel information to particular array section. At least two separate VRAM activities can be performed simultaneously to different parts of the array. Specifically, to write to one particular section of an array and to and for refreshing other parts of the VRAM. The overall read and write sequences can be shorter. When a particular pixel or memory cell has to be modified or update, only an associated SAM to the particular cell will be activated. This SAM will now only affect the column lines associated with that section of the array containing the activated SAM.

Abstract: A precharge circuit which is deactivated once a word line driver is activated. Specifically, a low output signal created by the selected driver is fed back to the precharge circuit to deactivate the precharge circuit during activation of a chosen word line.

Abstract: An etch mask having a narrow spacer layer self-aligned and adjacent to a first portion of an inorganic first layered segment. An inorganic second layered segment comprises a portion of the etch mask and encompasses a perimeter of the first layered segment and is distanced from the first layered segment by a distance equal to a thickness of the narrow spacer layer. A first portion of the second layered segment is adjacent to the narrow spacer layer. A void exists between second portions of the first and the second layered segments. The area of the substrate exposed by the etch mask of the invention, when etched, forms a trench whose width is limited only by the width of the void which is equal to the width of the narrow spacer layer. The narrowness of the narrow isolated trench formed using the etch mask of the invention maximizes die space.

Abstract: Presented is an integrated circuit chip including a random access memory (RAM) array, serial access memory (SAM), an arithmetic logic unit, a bidirectional shift register, and masking circuitry. The arithmetic logic unit, SAM, shift register, and masking circuitry are all as wide as one side of the RAM array, and are all communicable with each other via data transfer means. This allows wide word processing, user configurable for parallel processing. Bits masked by the masking circuitry are selectable by data in the bidirectional shift register, providing shiftable masking means. Random access and serial access are done through separate ports. The bidirectional shift register is optionally serially accessible. Methods of use are also presented.

Abstract: The invention is a monolithic memory device having a circuit and a method for decreasing the cell margin during a test mode. Decreasing the cell margin stresses the memory device during the test mode greater than a stress experienced during normal operation, thus test time can be decreased.

Abstract: A charge pump circuit and method for increasing a value of a supply potential. The charge pump circuit features a first stage circuit for generating an intermediate pumped potential greater than an input supply potential. The intermediate pumped potential becomes a supply potential for a portion of a second stage circuit. The second stage circuit generates a pumped output potential greater than the intermediate pumped potential. Both the first and second stage circuits have at least two capacitors, a small pump capacitor and a large pump capacitor. The first stage circuit of the invention supplies the increased intermediate pumped potential to those nodes which are used to charge the small pump capacitor of the second stage circuit. The input supply potential supplies the potential to those nodes which are used to charge the large pump capacitors of both stages and the small pump capacitor of the first stage circuit.

Abstract: An integrated circuit testing apparatus and method of testing. In a first embodiment an amplifier amplifies the difference in a reference integrated circuit (RIC) response and a device under test integrated circuit (DUTIC) response to an electrical stimulus. The electrical stimulus is provided at an input of the DUTIC and the RIC by a stimulus circuit. A analog comparator determines when the amplified differences exceeds an adjustable threshold value. The sensitivity of the comparator is adjustable and the desired threshold value is adjusted before testing begins. If the amplified difference exceeds the threshold value of the comparator an error signal is generated. The apparatus of the invention includes a presetable counter which generates a device fail signal if a predetermined number of error signals are generated by the comparator. An initialization circuit loads a selectable value into the counter to provide a variable number of allowable errors before a DUTIC fails the test.

Abstract: An inductively coupled plasma chamber having a capacitor electrode during cleaning of the plasma chamber.

Abstract: Silicon is employed as a reducing agent in an acid bath to adsorb noble metals present as contaminants in the acid. In the manufacture of silicon devices for electronic memory and other devices, polonium-210 is adsorbed by silicon getters to reduce soft error rate attributable to alpha particle emissions from the radioactive polonium. The noble metals in addition to polonium which can be plated onto silicon using the disclosed method are gold, silver, platinum, copper, palladium, mercury, selenium and bismuth.

Abstract: The invention is a circuit and method for providing a true tristate output at an output pad of a serial access memory device. The invention drives three distinct potentials to the output pad, two of which are potentials having high and low logic levels. The third potential, also referred to as the midrange potential, is a potential within a range of potentials defined by the potentials having the high and low logic levels. In an ideal case this potential is a midpoint potential midway between the potentials of the high and low logic level. The potential at the output pad is sensed by a sense circuit. The sense circuit creates a sense signal. Logic circuitry enabled by a one shot generator responds to the sense signal and disables the NOR function of an enable NOR gate and drives the output of the enable NOR gate to a potential that activates an output buffer. The output buffer drives the output pad to the desired midrange potential.

Abstract: The invention is a storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant. The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layer is formed in the recess. The process is then continued with a formation of an oxidation resistant conductive layer and the patterning thereof to complete the formation of the storage node electrode. Next a dielectric layer having a high dielectric constant is formed to overly the storage node electrode and a cell plate electrode is fabricated to overly the dielectric layer.