Abstract: A CMOS reference voltage generation circuit having a reference stage and a drive stage. Feedback is provided from the generated reference voltage to the reference stage. The inventive circuit is characterized by low standby current requirements, quick correction to deviations in the output voltage due to load variations, and quick response in generation of a new reference voltage when supply voltage transitions.

Abstract: The invention is a circuit for synchronizing the refresh cycles of a bank of self-refreshing interruptable DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing interruptable DRAM to its respective external refresh pin.

Abstract: Voltage sensing brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential.The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage.

Abstract: The apparatus of the present embodiment relates to iterative numerical techniques adapted for use in digital circuitry, such as floating point multipliers and floating point adder-subtractor units. Using the Newton methods of reciprocal and reciprocal square root computations of a value, several computational steps can be merged and performed with a single floating point multiplier unit. The preferred embodiment of the invention provides an improved apparatus for computing the reciprocal and reciprocal square root of an unknown value C using Newton's method. The improved method forms the reciprocal Newton iteration in the following two steps: ##EQU1## Each step requires only the use of a multiplier-accumulator, and is more efficient and hence computationally faster than prior methods.

Abstract: A low current substrate bias generator for regulating the potential of a substrate layer of an integrated circuit includes a sense element having an input for sensing the potential of the substrate. The substrate bias gates a PMOS transistor connected in a source follower configuration, being serially connected to a load element at its output and connected to ground at its drain. The PMOS transistor output is a control signal. The control signal is complemented by an inverter and the complement activates a charge pump that is coupled to the substrate layer or well that is desired to be regulated. The sense element includes the PMOS transistor and the load element. The sense element does not deplete or enhance the substrate potential but only provides substrate bias sensing and a subsequent control signal for activation and deactivation of the charge pump.

Abstract: The invention is a product and method for forming the same comprising a storage contact capacitor of a DRAM device wherein the storage node capacitor plate comprises first and second capacitor portions. The first portion is a self-aligned Tungsten and TiN core. In a first embodiment the second portion is a storage node polysilicon deposited and subjected to an insitu phosphorus diffusion doping. In a second embodiment the second portion comprises tungsten fingers formed elevationally and horizontally to overlie the tungsten and TiN core. Portions of TiN provide spacing between adjacent tungsten fingers. An upper polysilicon layer functions as the upper capacitor plate and is insulated from the lower capacitor plate by a dielectric layer.

Abstract: A multi-level potential generating circuit that brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential.The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage.

Abstract: An improved field implant process is disclosed wherein the field implant is performed after the field oxide isolation structure is fabricated by masking the active surface regions of the substrate with tungsten. The tungsten may be selectively deposited or blanket deposited. The energy of the field implant is controlled and adjusted to produce a maximum number of ions contiguous to a thinnest portion of field oxide with other portions being self-regulating.

Abstract: The machine method of the present embodiment relates to iterative numerical techniques adapted for use in digital circuitry, such as floating- point multipliers and floating point adder-subtractor units. Using the Newton method of reciprocal square root computation of a value, several computational steps can be merged and performed with a single floating point multiplier unit.

Abstract: The invention is a product and method for forming same comprising a storage contact capacitor of a dynamic random access memory (DRAM) device wherein at least two annular rings and a vertical fin of silicon are fabricated in a self-aligned opening parallel to and in contact with the contact area of the substrate. The rings and fin comprise the storage node of the capacitor, and the fin is substantially centered in the rings. The fin is fabricated by forming silicon in a channel remaining after alternating layers of silicon and oxide are deposited in the opening. The final deposition of oxide is subjected to a spacer etch thereby retaining the final oxide only on sidewalls of the channel. The final oxide then functions as a masking pattern for extending the channel by subjecting the alternating layers to subsequent etches. The silicon fin contacts all of the silicon rings thereby providing electrical communication between the fin and the rings.

Abstract: A DRAM cell having enhanced-capacitance attributable to the use of a textured structured polycrystalline silicon layer storage node capacitor plate. The present invention is particularly applicable to DRAM cells which employ a stacked capacitor design. Such designs generally employ a conductively-doped polycrystalline silicon layer as the storage node, or lower, capacitor plate. A microstructure is formed by anodizing the storage node plate layer in a solution of hydrofluoric acid to produce microstructures resembling elongated depressions in the storage node plate layer. This is followed by the deposition of a thin conformal (typically less than 100 Angstroms) silicon nitride layer which in turn is followed by the deposition of a second polycrystalline silicon (poly) layer, which functions as the capacitor field plate. Since the nitride layer is thin in comparison to the elongated depressions in the storage node plate layer, capacitive area is substantially augmented.

Abstract: Voltage sensing brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential. The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage.

Abstract: An output driver circuit of a DRAM is wired in a push-pull arrangement. A CMOS transistor arrangement provides a strong output signal. This transistor arrangement comprises the pull-up transistor circuit of the push-pull arrangement. A bootstrap circuit gates the NMOS of the CMOS causing an incremental increase in CMOS drain current.

Abstract: The invention is a method of forming a conductive contact plug and an interconnect line independent of each other. The contact plug is formed using laser planarization and a blanket etch back. The invention is also the contact plug thus formed. The contact plug and interconnect line may be fabricated with conductive materials having substantially similar methods of deposition. The integrity of the contact plug is enhanced using laser planarization.The process begins with a wafer having a dielectric layer, the upper surface of which has been planarized. A masking step defines a contact hole. An etch creates the contact hole which passes through the dielectric layer to a conductive region where contact is to be made. A first layer of conductive material is then deposited overlying the dielectric layer. A layer of material having an anti-reflective coating (ARC) (or a layer of material having a higher boiling point than the first layer) is deposited overlying the first layer.

Abstract: A method for fabricating a DRAM cell having enhanced-capacitance attributable to the use of a porous structured polycrystalline silicon layer storage node capacitor plate. The present invention is particularly applicable to DRAM cells which employ a stacked capacitor design. Such designs generally employ a conductively-doped polycrystalline silicon layer as the storage node, or lower, capacitor plate. A microstructure is formed by anodizing the storage node plate layer in a solution of hydrofluoric acid to produce microstructures resembling elongated pores in the storage node plate layer. This is followed by the deposition of a thin conformal (typically less than 100 Angstroms) silicon nitride layer which in turn is followed by the deposition of a second polycrystalline silicon (poly) layer, which functions as the capacitor field plate. Since the nitride layer is thin in comparison to the elongated pores in the storage node plate layer, capacitive area is substantially augmented.

Abstract: A process for forming within a masking layer a self-aligned annular opening having a width that is substantially narrower than the space width that can be created directly using the maximum resolution of available photolithography. The process involves the following steps: creation of a mask island using conventional photomasking and etching techniques, the perimeter of said island defining the inner perimeter of the perimetric annular opening; blanket deposition of a spacer layer, the thickness of which is equal to the desired width of the annular opening; a blanket deposition of a thick protective layer that is independently etchable over the spacer layer; planarization of the protection layer to or below the top of the spacer layer; and isotropically etching the exposed spacer layer to form a narrow annular opening exposing the substrate. At this point the exposed substrate may be trenched in order to isolate the area definedd by the island, or it may be fabricated in some other configuration.

Abstract: The invention is a compact multifunction logic circuit, offering low power operation and compact layout. It has utility in computer graphics processing circuitry. Internal and external data and inverse data inputs are provided to the three passthrough gates 21E, 21F and 21G. The circuit is designed so that one and only one of the passthrough gates 21E, 21F and 21G is activated at any given time. Therefore, even though all three passthrough gates 21E, 21F and 21G have inputs supplied by the outputs of NOR 22, XOR 20 and NAND 23 only one of the three gate outputs is passed to the final output node 19.

Abstract: A plasma etch process to anisotropically etch a sandwich structure of silicon dioxide, polycrystalline silicon, and silicon dioxide "in situ", that is, in a single etch chamber. The silicon dioxide is etched using a SF.sub.6 /CHF.sub.3 /He chemistry. The polycrystalline silicon is etched using a HBr/He chemistry. A non-erodible cathode is used. Tungsten silicide may replace the polycrystalline silicon. Silicon nitride may replace the silicon dioxide.