Abstract: An output driver circuit of a DRAM is wired in a push-pull arrangement. A CMOS transistor arrangement provides a strong output signal. This transistor arrangement comprises the pull-up transistor circuit of the push-pull arrangement. A bootstrap circuit gates the NMOS of the CMOS causing an incremental increase in CMOS drain current.

Abstract: The invention is a self-terminating helper flip-flop buffer circuit pertinent to a dynamic random access memory (DRAM) or static random access memory (SRAM) device. The invention turns off a device which is sourcing current to pull the data line low. The device is turned off when the potential on the low data line has transitioned to the trip point of the output data latch. The circuit of the invention senses the transition and provides the self terminating signal to the current source.

Abstract: The invention is the circuit and method for selecting a window of desired address locations to be written. A start address and a stop address activate a start and stop decoder output respectively. The active start and stop decoder output signals are rippled through start and stop ripple circuitry which enables the outputs electrically interposed between the start and stop addresses respectively. AND circuitry ensures that only the outputs interposed between the start and stop addresses are activated in addition to the start and stop decoder outputs. The activated outputs comprise the window of desired address locations to be written.

Abstract: The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The driving device is electrically interposed between the wordline and a reference node. The invention provides low power operation, and provides reliable wordline selection for circuits having supply potentials less than 5 volts.

Abstract: The invention is an apparatus for implementing a split read/write operation in a multiple write enable dynamic random access memory (DRAM) device. A split read/write operation is an operation where the data in at least one bank is read while the data is being written to at least one remaining bank, all banks accessed by the same address. The DRAM device of the invention is also capable of a write to at least one bank and a read to at least one bank. In instances where all of the banks are not written, the banks not being written are refreshed; and in instances where all of the banks are not being read, the banks not being read are masked for a write. The invention also provides individual masking of selected memory arrays in both write and read operations.

Abstract: In the preferred embodiment of the present invention flash write, a simultaneous and substantially identical write operation to a selected plurality of memory cells, is performed by splitting the pull up of the p sense amplifier transistors. The p sense amplifier transistor on digit is connected to V.sub.cc at its drain through a first pull up transistor and the p sense amplifier transistor on digit bar is connected to V.sub.cc at its drain through a second pull up transistor. A logic circuit generates control logic that actuates either both pull up transistors to initiate a typical read/write operation of a single memory cell or actuates one of the two pull up transistors to initiate a flash write to all of the memory cells on the selected wordline.

Abstract: A multi-level potential generating circuit that brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential. The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage.

Abstract: The invention features a circuit wherein a serially connected transistor and anti-fuse element are biased for current to flow in a first direction or the current flows in the first direction during a programming operation and biased for a current to flow in a second direction or current is flowing in the second direction during a normal circuit operation, such as a read operation, wherein the first and second directions are opposite of one another. Thus the invention facilitates the use of a low programming potential while minimizing leakage current.

Abstract: The invention is a coupling circuit for quickly increasing the differential potential between non-selected bit lines and selected bit lines in the case where the digital data has a high logic state, while retaining a valid differential potential for the case where the digital data has a low logic state. The circuit comprises a true and a complement coupling line typically held at an equilibrate potential substantially equal to the equilibrate potential of the bit lines. A coupling capacitor is electrically interposed between each of the true bit lines and the true coupling line and a coupling capacitor is electrically interposed between each of the complement bit lines and the complement coupling line. During cell selection the potential of the coupling line in electrical communication with the non-selected bit lines is switched to a reference potential by select coupling line circuitry.

Abstract: The invention is an automatic precharge circuit featuring precharge devices each of which is interposed between a high voltage node, connectable to a supply potential, and a serial node. The precharge devices are gated automatically by a primary predecode signal of a decode portion of the row decoder. Power is conserved since the serial nodes are passively pulled to the supply potential through the precharge devices. The invention increases speed and provides error free wordline selection.

Abstract: The invention is a method for implementing a split read/write operation in a multiple write enable dynamic random access memory device. A split read/write operation is an operation where the data in at least one bank is read while the data is being written to at least one remaining bank, all banks accessed by the same address. The method of the invention also implements writes and reads to all of the banks, a write to at least one bank, and a read to at least one bank. In instances where all of the banks are not written, the banks not being written are refreshed; and in instances where all of the banks are not being read, the banks not being read are masked for a write. The invention also provides individual masking of selected memory arrays in both write and read operations.

Abstract: The invention is an output driver circuit of a dynamic random access memory (DRAM) wherein the output driver is wired in a push-pull configuration. The push-pull configuration comprises a pull-up portion and a pull-down portion serially connected at an output node. The pull-up portion comprises a an n-channel metal oxide semiconductor (NMOS) transistor having a gate potential determined by a programmable circuit. In the preferred embodiment the programmable circuit provides a potential to the gate node of the NMOS that is directly proportional to the supply potential until a maximum programmed gate potential is reached. The programmable circuit maintains the maximum programmed gate potential for further increases in the supply potential. The pull-down portion comprises a pull-down NMOS transistor interposed between the output node and ground. The pull-down NMOS transistor is controlled by a pull-down signal on the gate node. When actuated the pull-down transistor provides a low logic level at the output node.

Abstract: A dynamic memory device exhibits a sleep mode of operation, entered in response to a single externally-applied signal which need not be cycled. While in this sleep mode, the device does not respond to or require any of the usual DRAM control signals such a RAS, CAS, write enable, address inputs, data inputs, etc., so all of these signals may be in a quiescent state. An internal refresh counter is used to generate row addresses while in the sleep mode, and timing for the internal refresh is provided by an internal oscillator. The memory device cycles through a sequence of row addresses for refresh while in this sleep mode, using an internal refresh address counter, and this sequence may be maintained without interruption if the sleep mode is reentered within a normal refresh period after exiting the sleep mode.

Abstract: A dynamic random access memory (DRAM) storage cell having a storage contact capacitor comprising a tungsten and TiN storage node capacitor plate and the method for fabricating the same. At least a portion of the storage node capacitor plate is formed vertically in the DRAM. The TiN is controllably etched to increase the area of the storage node capacitor plate. An upper poly layer functions as the cell plate and is insulated from the storage node capacitor plate by a dielectric layer.

Abstract: A voltage generation circuit reduces power consumption by providing a regulator circuit wherein the current in an inverter leg of the generator is proportional to the current in a sense element portion of the regulator. The inverter leg comprises n- and p-channel transistors which are gated by signals from the sense element portion.

Abstract: A process for forming within a masking layer self-aligned narrow isolated spacings having a width that is substantially narrower than the space width that can be created directly using the maximum resolution of available photolithography and the process for utilizing said masking layer to form narrow isolated trenches in a semiconductor substrate.

Abstract: A dynamic random access memory (DRAM) cell having a corrugated storage contact capacitor for enhancing capacitance. A noncritical alignment is effected between the substrate contact area and the lower capacitor plate by using an etch stop layer to protect wordlines, field-effect transistors (FETs), and field oxide regions during the patterning and etching of storage capacitor regions. The corrugated storage contact capacitor is fabricated by depositing alternating layers of dielectric materials having either substantially different etch rates or wet etch selectivity one toward the other. The layers are isotropically etched and a cavity having corrugated sidewalls is provided. A doped poly layer is deposited to function as the storage-node capacitor plate. The deposition of a dielectric layer is followed by an insitu-doped poly layer deposited to form the upper capacitor plate. The capacitor thus formed is typified as having the storage-node capacitor plate self-aligned to the contact area of the substrate.

Abstract: The invention synchronizes the refresh cycles of a bank of self-refreshing DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing DRAM to its respective external refresh pin. An arbitration circuit determines the self-refreshing DRAM having a fastest timing sequence, maintains that timing sequence and shuts down all timing circuits having slower timing sequences. The arbitration circuit of each self-refreshing DRAM provides a refresh signal to each respective refresh circuit.

Abstract: The invention is a circuit synchronizing the refresh cycles of a bank of self-refreshing DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing DRAM to its respective external refresh pin. An arbitration circuit determines the self-refreshing DRAM having a fastest timing sequence, maintains that timing sequence and shuts down all timing circuits having slower timing sequences. The arbitration circuit of each self-refreshing DRAM provides a refresh signal to each respective refresh circuit.

Abstract: The machine method of the present embodiment relates to iterative numerical techniques adapted for use in digital circuitry, such as floating point multipliers and floating point adder-subtractor units. Using the Newton method of reciprocal computation of a value, several computational steps can be merged and performed with a single floating point multiplier unit. The preferred embodiment of the invention provides an improved method for computing the reciprocal of an unknown value C using Newton's method. The improved method forms the reciprocal Newton iteration in the following two steps:1. cx.sub.m form the product of x.sub.m and c.2. x.sub.m {2-cx.sub.m } form the product and difference simultaneously. Each step requires only the use of a multiplier-accumulator, and is more efficient and hence computationally faster than prior methods.