Abstract: An external fiber optic cable is snap fit onto the connector of the integrated circuit package, light passes from an optical fiber in the external cable, through the first optical fiber and to the reflecting surface where the light is reflected by the reflecting surface so that it is incident on the photodetector whereas the photodetector converts the light into an electrical signal and the electrical signal is then communicated via a micro pad structures from the optoelectronic die.

Abstract: A mail server collects messages from a number of user accounts and presents them to the user from a single location. The user can set the mail server to block unwanted messages and to forward others to various receiving devices, including mobile telephones and pagers. Forwarded messages are automatically reformatted for the receiving device, while a copy of the original message is retained. The retained copy can be viewed later if the user is interested in message content that was not available to the wireless device. The user can also use the wireless device to forward the original message to another receiving device. In the case of forwarding, the saved original message and not the reformatted message is sent to the forwarding address. Some embodiments include an email agent that automatically pushes messages from intranet clients to the mail server through a firewall, thereby enabling the mail server to consolidate messages from intranet and Internet sources.

Abstract: A Network Interface device (NI device) coupled to a host computer receives a multi-packet message from a network (for example, the Internet) and DMAs the data portions of the various packets directly into a destination in application memory on the host computer. The address of the destination is determined by supplying a first part of the first packet to an application program such that the application program returns the address of the destination. The address is supplied by the host computer to the NI device so that the NI device can DMA the data portions of the various packets directly into the destination. In some embodiments the NI device is an expansion card added to the host computer, whereas in other embodiments the NI device is a part of the host computer.

Abstract: A die assembly contains multiple stacked dice bonded together by a large number of metal posts. A first die has a plurality of metal posts oriented orthogonally to a planar surface of the first die. The metal posts protrude from the first die out beyond the surface. Similarly, a second die also has a plurality of metal posts protruding from a surface. The first die is coupled to the second die in an oxygen-free atmosphere such that each protruding metal post of the first die contacts a protruding metal post of the second die. By applying pressure, cold welds are formed between corresponding metal posts of the first and second dice. The first die and the second die are held together by the metal posts without an adhesive. In one embodiment, some of the metal posts do not conduct signals between the first and second dice.

Abstract: A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the substrate material of the device wafer. The source and drain regions of the transistor extend into the well region. After attachment of the supporting structure, the device wafer is thinned from the back side until the bottom of the well region is reached. To reduce source and drain junction capacitances, etching can continue until the source and drain regions are reached. In one embodiment, all of the well-to-substrate junction is removed in a subsequent etching step, thereby reducing or eliminating the well-to-substrate junction capacitance of the resulting transistor. Resistance between the well electrode and the transistor channel is reduced because the well contact is disposed on the back side of the device wafer directly under the gate of the transistor.

Abstract: An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU.

Abstract: An improved CLB architecture, wherein the use of dedicated AND gates to generate a carry chain input signal facilitates low latency multiplication and makes efficient use of four-input function generators. In one embodiment of the invention, when multiplication using a binary addition tree algorithm is used, AND gates to implement single-bit multiplication are provided within the available function generators and duplicated in a dedicated AND gate accessible outside the corresponding function generator as a carry-chain input signal. In another embodiment, carry chain multiplexers can be selectively configured as AND or OR gates to facilitate certain arithmetic or comparison functions for the outputs of a plurality of function generators.

Abstract: A host CPU runs a network protocol processing stack that provides instructions not only to process network messages but also to allocate processing of certain network messages to a specialized network communication device, offloading some of the most time consuming protocol processing from the host CPU to the network communication device. By allocating common and time consuming network processes to the device, while retaining the ability to handle less time intensive and more varied processing on the host stack, the network communication device can be relatively simple and cost effective. The host CPU, operating according to instructions from the stack, and the network communication device together determine whether and to what extent a given message is processed by the host CPU or by the network communication device.

Abstract: At least one intelligent network interface card (INIC) is coupled to a host computer to offload protocol processing for multiple network connections, reducing the protocol processing of the host. Plural network connections can maintain, via plural INIC ports and a port aggregation switch, an aggregate connection with a network node, increasing bandwidth and reliability for that aggregate connection. Mechanisms are provided for managing this aggregate connection, including determining which port to employ for each individual network connection, and migrating control of an individual network connection from a first INIC to a second INIC.

Abstract: A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The CPD provides a fast-path that avoids protocol processing for most large multipacket messages, greatly accelerating data communication. The CPD also assists the host CPU for those message packets that are chosen for processing by host software layers. A context for a message is defined that allows DMA controllers of the CPD to move data, free of headers, directly to or from a destination or source in the host. The context can be stored as a communication control block (CCB) that is controlled by either the CPD or by the host CPU. The CPD contains specialized hardware circuits that process media access control, network and transport layer headers of a packet received from the network, saving the host CPU from that processing for fast-path messages.

Abstract: A network interface device provides a fast-path that avoids most host TCP and IP protocol processing for most messages. The host retains a fallback slow-path processing capability. In one embodiment, generation of a response to a TCP/IP packet received onto the network interface device is accelerated by determining the TCP and IP source and destination information from the incoming packet, retrieving an appropriate template header, using a finite state machine to fill in the TCP and IP fields in the template header without sequential TCP and IP protocol processing, combining the filled-in template header with a data payload to form a packet, and then outputting the packet from the network interface device by pushing a pointer to the packet onto a transmit queue. A transmit sequencer retrieves the pointer from the transmit queue and causes the corresponding packet to be output from the network interface device.

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.

Abstract: A phase-locked loop (PLL) having a wide range of oscillator output frequencies and a wide range of loop divider values is realizable in integrated form because the total capacitance of its loop filter is small. The PLL includes a first phase detector, a second phase detector, a programmable tapped-delay-line oscillator, a divide-by-M loop divider, and a programmable on-chip loop filter. The programmable filter is programmed to realize one of many loop filters. In a first step, oscillator output is fed back via the loop divider to the first phase detector. Oscillator frequency is decremented by changing tap selection inside the oscillator until the first phase detector determines that the frequency of the signal fed back via the loop divider (divide-by-M) is smaller than the frequency of an input signal. The tap control at which this frequency lock condition occurred, along with value M, is then used to determine which of the many loop filters will be used in a phase lock step.

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells.

Abstract: An FPGA has an on-chip processor that reads configuration data onto the FPGA and controls the loading of that configuration data into FPGA configuration memory cells. After FPGA power-up, the processor reads a configuration mode code from predetermined terminals of the FPGA. If the configuration mode code has a first value, then the processor executes a first configuration program so that configuration data is received onto the FPGA in accordance with a first configuration mode. If the configuration mode code has a second value, then the processor executes a second configuration program so that configuration data is received onto the FPGA in accordance with a second configuration mode. The configuration programs can be stored in metal-mask ROM on-chip so they can be changed without re-laying out the remainder of the FPGA. Providing multiple configuration programs allows the FPGA to support multiple configuration modes using the same processor hardware.

Abstract: A programmable logic device makes better use of its I/O terminals (for example, package pins) by both amplitude and phase encoding a stream of multi-bit digital values into a single DATA signal. Information in the DATA signal is encoded into four different voltage levels and four different phases. The DATA signal is communicated from the FPGA via just one I/O terminal, as opposed to many I/O terminals. An amplitude/phase encoder is described that includes a delay line in a delay-locked loop, as well as two other delay lines that are slaved to the delay line of the delay-locked loop. The slaved delay lines are used to phase encode the information into the DATA signal. An amplitude/phase decoder is also described that enables the programmable logic device to receive and decode such a DATA signal. The amplitude/phase decoder includes a delay line in a delay-locked loop, as well as two other delay lines that are slaved to the delay line of the delay-locked loop.

Abstract: An integrated circuit receives an external clock signal and generates therefrom a clock signal that is supplied to a plurality of external devices. A delay-locked loop (DLL), a balanced clock tree, and a plurality of interface cells on the integrated circuit function together to supply the clock signal to the plurality of external devices such that the clock signal at each of the external devices is deskewed with respect to the external clock signal. Board level design is simplified because no balanced clock tree is needed to route the clock signal from the integrated circuit to the external devices, rather each external device is coupled to a corresponding one of the interface cells via a separate external connection. Each of these external connections has an equal propagation delay. One of the interface cells supplies the clock signal back to a reference signal input of the DLL via an external connection.

Abstract: An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU.

Abstract: A host CPU runs a network protocol processing stack that provides instructions not only to process network messages but also to allocate processing of certain network messages to a specialized network communication device, offloading some of the most time consuming protocol processing from the host CPU to the network communication device. By allocating common and time consuming network processes to the device, while retaining the ability to handle less time intensive and more varied processing on the host stack, the network communication device can be relatively simple and cost effective. The host CPU, operating according to instructions from the stack, and the network communication device together determine whether and to what extent a given message is processed by the host CPU or by the network communication device.

Abstract: A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU.