Abstract: A phase-locked loop (PLL) having a wide range of oscillator output frequencies and a wide range of loop divider values is realizable in integrated form because the total capacitance of its loop filter is small. The PLL includes a first phase detector, a second phase detector, a programmable tapped-delay-line oscillator, a divide-by-M loop divider, and a programmable on-chip loop filter. The programmable filter is programmed to realize one of many loop filters. In a first step, oscillator output is fed back via the loop divider to the first phase detector. Oscillator frequency is decremented by changing tap selection inside the oscillator until the first phase detector determines that the frequency of the signal fed back via the loop divider (divide-by-M) is smaller than the frequency of an input signal. The tap control at which this frequency lock condition occurred, along with value M, is then used to determine which of the many loop filters will be used in a phase lock step.

Abstract: An analog-to-digital converter (ADC) is realized in a field programmable gate array (FPGA) without adding special dedicated analog circuitry. In a digital application, a comparator in an interface cell of the FPGA compares an incoming digital signal to a reference voltage. Adjusting of the reference voltage allows the interface cell to support different digital I/O standards. In one embodiment, the comparator is not used for this digital purpose, but rather is used as a comparator in an ADC. A flash ADC is realized by using the comparators of numerous interface cells as the comparators of the flash ADC. Conversion speed is increased by reducing the impedance of the analog signal input path. An on-chip resistor string is provided so that the flash ADC can be realized without external components. In another embodiment, the comparator of the interface cell is the comparator of a successive approximation ADC.

Abstract: A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU.

Abstract: The maximum propagation speed of an electrical signal travelling on a conductor in an integrated circuit is limited by the dielectric constant of the dielectric material surrounding the conductor. Rather than transmitting an electrical signal through a conductor that is surrounded with a dielectric material having a dielectric constant of two or more, the signal is propagated as an electromagnetic wave through air at a much higher speed across the surface of the integrated circuit. In one embodiment, a radio frequency (RF) signal is passed into an integrated circuit package via a transmission line. The transmission line supplies the RF signal to a waveguide-like structure disposed above the integrated circuit inside the package. The RF signal propagates as an electromagnetic wave through air in the waveguide structure across the upper surface of the integrated circuit.

Abstract: The maximum propagation speed of an electrical signal travelling on a conductor in an integrated circuit is limited by the dielectric constant of the dielectric material surrounding the conductor. Rather than transmitting an electrical signal through a conductor that is surrounded with a dielectric material having a dielectric constant of two or more, the signal is propagated as an electromagnetic wave through air at a much higher speed across the surface of the integrated circuit. In one embodiment, a radio frequency (RF) signal is passed into an integrated circuit package via a transmission line. The transmission line supplies the RF signal to a waveguide-like structure disposed above the integrated circuit inside the package. The RF signal propagates as an electromagnetic wave through air in the waveguide structure across the upper surface of the integrated circuit.

Abstract: A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multipacket messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU.

Abstract: An analog-to-digital converter (ADC) is realized in a field programmable gate array (FPGA) without adding special dedicated analog circuitry. In a digital application, a comparator in an interface cell of the FPGA compares an incoming digital signal to a reference voltage. Adjusting of the reference voltage allows the interface cell to support different digital I/O standards. In one embodiment, the comparator is not used for this digital purpose, but rather is used as a comparator in an ADC. A flash ADC is realized by using the comparators of numerous interface cells as the comparators of the flash ADC. Conversion speed is increased by reducing the impedance of the analog signal input path. An on-chip resistor string is provided so that the flash ADC can be realized without external components. In another embodiment, the comparator of the interface cell is the comparator of a successive approximation ADC.

Abstract: A clock signal is driven at one point onto a clock bus of an integrated circuit by a driver circuit. Oscillators are coupled along the length of the clock bus. The oscillators are all loosely coupled to one another through the clock bus such that all the oscillators oscillate together at the frequency of the clock signal. The oscillators add energy to the clock signal on the clock bus locally so that all the energy required to sustain the clock signal does not have to come from the point of origin. By reducing current flow down the clock bus across the series resistance of the clock bus, limits on propagation speed due to the series resistance of the clock bus are avoided. In one embodiment, less than 15 milliwatts is consumed to “propagate” a 1.36 gigahertz clock signal a distance of two centimeters down a clock bus of an integrated circuit at a propagation speed of approximately 2.1×107 meters per second.

Abstract: A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multipacket messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the IMC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU.

Abstract: The maximum propagation speed of an electrical signal travelling on a conductor in an integrated circuit is limited by the dielectric constant of the dielectric material surrounding the conductor. Rather than transmitting an electrical signal through a conductor that is surrounded with a dielectric material having a dielectric constant of two or more, the signal is propagated as an electromagnetic wave through air at a much higher speed across the surface of the integrated circuit. In one embodiment, a radio frequency (RF) signal is passed into an integrated circuit package via a transmission line. The transmission line supplies the RF signal to a waveguide-like structure disposed above the integrated circuit inside the package. The RF signal propagates as an electromagnetic wave through air in the waveguide structure across the upper surface of the integrated circuit.

Abstract: Certain digital logic elements within the core of a field programmable integrated gate array (FPGA) require relatively large spikes of supply current when they switch. Local integrated metal plate bypass capacitors are provided in the core of the FPGA near the digital logic elements. The local integrated bypass capacitors provide the digital logic elements with a substantial portion of the required spikes of supply current. The magnitude of supply current spikes drawn over resistive and/or inductive power leads from the edges of the FPGA is therefore reduced and associated drops in supply voltage at the core are reduced.

Abstract: A system and method for routing signals to function blocks of a programmable logic device (PLD) via an interconnect multiplexer (XMUX). All available paths from an interconnect multiplexer input resource to an interconnect multiplexer output resource are first identified. Signals are assigned to XMUX paths in order of number of fanouts to function blocks. The signal required by the most function blocks is assigned first. The costs of the XMUX paths relative to the signal to be assigned are determined, and the signal is assigned to the path having the least cost. The process is repeated until all the signals are assigned. A recovery method uses augmenting paths to assign signals if all the signals could not be assigned using least cost paths assignment.

Abstract: Certain digital logic elements within the core of a field programmable integrated gate array (FPGA) require relatively large spikes of supply current when they switch. Local integrated metal plate bypass capacitors are provided in the core of the FPGA near the digital logic elements. The local integrated bypass capacitors provide the digital logic elements with a substantial portion of the required spikes of supply current. The magnitude of supply current spikes drawn over resistive and/or inductive power leads from the edges of the FPGA is therefore reduced and associated drops in supply voltage at the core are reduced.

Abstract: A storage apparatus facilitates the storage of items inside a handle (for example, a handle portion of a bicycle handlebar). The storage apparatus includes a cylindrical storage member coupled to an engaging device for removably engaging the handlebar. An item to be stored (for example, a tire lever) is placed in the cylindrical storage member, the cylindrical storage member is slid into the hollow open end of a handle bar until the engaging device plugs the end of the handlebar. The engaging device is then made to engage the handlebar (for example, by expanding circumferentially to frictionally engage the inside surface of the handlebar) to secure the storage member in place inside the handlebar. The item is retrieved by disengaging the engaging device from the handlebar, sliding the storage member out of the handlebar, opening the storage member, and removing the item.

Abstract: A peripheral coupled to a SCSI bus is isolated using a SCAM isolation step and the original SCSI identification bits (32 bytes) are read from the isolated peripheral into a host adapter. The host adapter then generates a relatively small number (for example, 4 bytes) of identification bits from the relatively large number of original SCSI identification bits. The small number of SCSI identification bits is stored in a non-volatile memory of the host adapter such that the memory location of the SCSI identification bits of a particular peripheral corresponds with the logical system identifier of that peripheral. Even if peripherals are removed from the bus and/or added to the bus, the small number of SCSI identification bits for a peripheral previously on the bus is redetermined and located in non-volatile memory of the host adapter so that the logical system identifier of the peripheral previously coupled to the bus is not changed.