Patents Represented by Attorney Theodore D. Lindgren
  • Patent number: 5858839
    Abstract: This invention provides a cost-effective, easy-to-integrate Flash EPROM cell array. Starting with a substrate (31) of first conductivity-type, a first diffusion (30) of second conductivity-type forms the sources (11), and the connections between sources, of all of the memory cells (10) of the array. A second diffusion (32) of first conductivity-type forms the channel of at least one memory cell (10) in the array. A floating gate (13) and a control gate (14) of that memory cell (10) are located over, and insulated from, a junction of the first diffusion and the second diffusion. A third diffusion (33) of second conductivity-type is isolated in the second diffusion (32) to form the drain (12) of the memory cell (10). During operation, only positive voltages may be used for programming and erasing of the cells (10), thus eliminating the need for negative voltages and for triple-well diffusions. The cell array of this invention requires little or no current for Fowler-Nordheim erase operation.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: January 12, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Cetin Kaya, Kemal Tamer San
  • Patent number: 5796296
    Abstract: This invention is a voltage divider circuit having an input voltage at a first terminal (V.sub.IN) and an output voltage at a second terminal (V.sub.OUT). The circuit includes a parallel-connected first resistor (R.sub.1) and first capacitor (C.sub.1) coupled between the first and second terminals (V.sub.IN,V.sub.OUT) and a parallel-connected second resistor (R.sub.2) and second capacitor (C.sub.2) coupled between the second terminal (V.sub.OUT) and a reference (V.sub.REF). The ratio of the ohmic value of the second resistor (R.sub.2) to the sum of the ohmic values of the first and second resistors (R.sub.1,R.sub.2) is substantially equal to the ratio of the value in farads of the first capacitor (C.sub.1) to the sum of the values in farads of the first and second capacitors (C.sub.1,C.sub.2).
    Type: Grant
    Filed: October 7, 1996
    Date of Patent: August 18, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Steven V. Krzentz
  • Patent number: 5787091
    Abstract: The circuit of this invention includes a programmable circuit (PC) for storing an internal address and for producing logic levels (LL1, etc.) determined by that internal address and includes a first comparison circuit (CC1) and a second comparison circuit (CC2). The first comparison circuit (CC1) responds to the logic levels (LL1, etc.) representative of that internal address and to a first address signal (CA0, etc.) to generate a first match signal (CRFSN) determined by matching of the internal address and the first address signal (CA0, etc.). The second comparison circuit (CC2) responds to the logic levels (LL1) and to a second address signal (SF0, etc.) to generate a second match signal (SRSJN) determined by the matching of the internal address and the second address signal (SF0, etc.).
    Type: Grant
    Filed: June 13, 1995
    Date of Patent: July 28, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: David V. Kersh, III
  • Patent number: 5773997
    Abstract: Reference circuitry RC includes a current-sensing translator M5-M7, MX connected to a current reference source RS. The outputs O1, O2, etc. of the current-sensing translator M5-M7, MX are mirrored into one or more sense amplifiers SA1,SA2 of sensing circuitry SC. The current-sensing translator M5-M7, MX permits the current from the current reference source RS to be mirrored to multiple sense amplifiers SA1,SA2 at a predetermined ratio.
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: June 30, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Harvey J. Stiegler
  • Patent number: 5753952
    Abstract: An integrated circuit memory cell (10) is formed with a P-N junction polycrystalline floating gate (13) with a lightly boron doped on the source side (13B) and a heavily arsenic or phosphorous doped on the drain side (13A) plus the channel region (Ch) . The cells (10) are formed in an array at a face of a semiconductor body (22), each cell including a source (11) and including a drain (12). An improved over-erase characteristic is achieved by forming a P-N junction (JU) in the floating gate (13). Use of a P-N junction (JU) in polycrystalline floating gate (13) prevents the cell (10) from going into depletion, causes a tighter distribution of erased threshold voltages V.sub.T, and improves device life because fewer electrons travel through the gate oxide (30).
    Type: Grant
    Filed: September 22, 1995
    Date of Patent: May 19, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Freidoon Mehrad
  • Patent number: 5740105
    Abstract: An EPROM or flash EEPROM, which has an array of single-transistor, stacked-gate, memory cells. Active areas for transistor elements are in columns up and down the array, with columns being isolated by thick field oxide strips (220). Word lines (236) and source lines (212) run across the array. Bit lines (216) run along the active area columns to connect transistor drains (218). Bit lines are perpendicular to word lines. Each stacked gate includes a control gate (232) and a floating gate (230), with the latter having a top portion (230b) and a bottom portion (230a) that are separately deposited and etched. The bottom portion (230a) is etched in strips along the active area columns, and define the gate width of each cell. The top portion (230b) overlaps the bottom portion (230a) to improve capacitance between control gate (232) and floating gate (230).
    Type: Grant
    Filed: October 17, 1996
    Date of Patent: April 14, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Manzur Gill
  • Patent number: 5719880
    Abstract: The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro-instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a micro-instruction decoder with BILBO control (MID/BC), a test input multiplexer (TIM) to test control signals, an optional status output register (SOR) to generate control signals, and a subroutine stack (SS) to allow function calls. A program counter (PC) takes an index signal from the micro-instruction decoder with BILBO control (MID/BC) and a signal from the program counter multiplexer (PCM), and from those signal, generates a next microcode address. Complex program, erase, and compaction instructions for the integrated-circuit memory are implemented using a relatively small number of control-read-only-memory locations and using a relatively small surface area on the memory chip.
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: February 17, 1998
    Assignee: Texas Instruments Incorporated, a Delaware Corporation
    Inventor: Yu-Ying Jackson Leung
  • Patent number: 5694073
    Abstract: A supply-voltage detecting stage (11) that supplies first and second reference currents (I.sub.REFP and I.sub.REFN) which vary with the supply voltage (V.sub.cc) and are coupled by first and second gain stages (12A and 12B), respectively, to first and second temperature-detecting stages (13A and 13B), respectively. First and second temperature-detecting stages (13A and 13B) increase the coupled reference currents (I.sub.REFP and I.sub.REFN), respectively, to compensate for temperature increase through use temperature-sensitive, long-channel transistors (M34-M37 and M42-M45), supplying temperature and supply-voltage compensated output bias voltages at output terminals (MIRN and MIRP).
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: December 2, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy J. Coots, Phat C. Truong, Sung-Wei Lin, Tim M. Coffman, Ming-Bo Liu, Ronald J. Syzdek
  • Patent number: 5675546
    Abstract: The on-chip endurance test (Autocycle) and the parametric characterization test (Auto VccMax/Min) of this invention save test time and hardware by performance automatically on the memory chip upon transmittal of a single command (CONTROL CODE) to the chip from the tester. The automated test procedures of this invention run faster because the on-chip tester requires fewer externally issued commands (CONTROL CODEs) and requires fewer external status checks. The procedures of this invention permit the external tester to have a smaller number of input/output pins (CONTROL), decreasing the cost of the external test hardware. Specifically, the endurance test (Autocycle), automatically cycles the memory chip through any combination of programming, erasing, and/or compaction operations until either a failure has been detected or the required number of the test cycles has been completed.
    Type: Grant
    Filed: June 7, 1996
    Date of Patent: October 7, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Yu-Ying Jackson Leung
  • Patent number: 5668769
    Abstract: The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to transient currents. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pulses from powering down internal direct-current paths. At the same time, the output driver high impedance functionality of the chip-disable signal is preserved.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: September 16, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Tim M. Coffman, Ronald J. Syzdek, Timothy J. Coots, Phat C. Truong, Sung-Wei Lin
  • Patent number: 5659500
    Abstract: A nonvolatile memory array has a plurality of diffused horizontal source lines (17), each source line (17) positioned between a pair of parallel horizontal stack conductors (ST). The plurality of the diffused horizontal source lines (17) are connected to at least one common vertical source conductor (17a). The common vertical source conductor (17a) includes continuous diffused regions (11) under each of said pair of parallel horizontal stack conductors (ST). In addition, the common vertical source conductor (17a) includes a metal conductor coupled to the continuous diffused regions at contacts (SC) located between the pairs of parallel horizontal stack conductors (ST). As a result, the stack conductors (ST) are straight. The straight-stack conductor (ST) configuration allows use of less space between a vertical source conductor (17a) and adjacent drain-column lines (18) and eliminates any need for use of vertical columns of dummy cells (10).
    Type: Grant
    Filed: September 26, 1995
    Date of Patent: August 19, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Freidoon Mehrad
  • Patent number: 5657268
    Abstract: In a multi-sector nonvolatile memory array in which each memory cell has a drain coupled to a bitline, each memory cell of each sector has a source coupled to a common array-source line, each memory cell in a row of the first sector has a control gate coupled to a wordline and each memory cell of a row in another sector has a control gate coupled to that wordline, a method for programming a memory cell in one sector of said method includes connecting at least the second common array-source line to each bitline coupled to drains of columns of memory cells in the another sector, then biasing at a positive voltage both the common array-source line and the bitlines coupled to drains of memory cells in columns of the another sector, and then applying a programming voltage to the selected wordline coupled to the control gate of the selected cell in the first sector.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: August 12, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Phat C. Truong, Sung-Wei Lin
  • Patent number: 5654219
    Abstract: A method for forming poly-silicide conductors (CG,GAP) on a semiconductor device (10) includes forming a layer (14) of doped polysilicon over a region of the device (10), then depositing a layer (15) of refractory metal on the layer (14) of doped polysilicon. The layer (14) of doped polysilicon and the layer (15) of refractory metal are then annealed to form a poly-silicide layer (PSL). The poly-silicide layer (PSL) is then etched to form the poly-silicide conductors (CG,GAP).
    Type: Grant
    Filed: February 7, 1996
    Date of Patent: August 5, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Michael L. Huber
  • Patent number: 5646887
    Abstract: Low-voltage-correcting bias circuitry for a sense amplifier includes first, second and third N-channel transistors. The channel of the first transistor couples a current mirror to the input terminal of the amplifier and the gate of the second transistor, the channel of the second transistor couples the gate of the first transistor to a reference terminal. The channel of the third transistor couples the supply voltage to the gate of the first transistor. The gate of the third transistor is coupled to a reference voltage. A P-channel transistor has a channel coupling the supply voltage to the gate of the first transistor. The gate of the P-channel transistor is coupled to a low-voltage-sensing signal. Pre-charge circuitry includes a nonvolatile memory cell and fourth, fifth and sixth N-channel transistors. The channel of the fourth transistor is in series with the channel of the memory cell. The channel of the fifth transistor couples the channel of the memory cell to the input of the sense amplifier.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: July 8, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Phat C. Truong, Tim M. Coffman
  • Patent number: 5646894
    Abstract: The circuit of this invention improves significantly the programming speed of a Flash EPROM. The circuit includes a detector circuit (DC) using a pre-charge capacitor (C1), capacitor dividers [(C1/(C1+C2) and C3/(C2+C3)] and a voltage comparator (COMP) to signal a control logic circuit (CLC) when the programming voltage is within supply voltage (V.sub.cc) of its final value. At that point the control logic circuit (CLC) boosts the voltage on one terminal of a boost capacitor (BC) by the value of the supply voltage (V.sub.cc). The other terminal (XDD) of the boost capacitor (BC) furnishes the boosted programming voltage for the Flash EPROM.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: July 8, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Sung-Wei Lin, Tim M. Coffman, Ronald J. Syzdek
  • Patent number: 5636226
    Abstract: A fault sensing circuit for detecting the state of at least one latch controlled by at least one control signal is provided. The circuit comprises an additional latch also controlled by the same control signal and receiving an input of a known value. The output of the additional latch is coupled to an I/O pin where an external circuit may monitor its logic state to determine the occurrence of a fault.
    Type: Grant
    Filed: January 9, 1995
    Date of Patent: June 3, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Phat C. Truong, John F. Schreck
  • Patent number: 5636162
    Abstract: A procedure for erasing a Flash EPROM array (AR) includes applying a series of erase pulses to all of the subarrays (S1, S2, etc.) of a Flash EPROM array (AR) simultaneously. Between each erase pulse, the memory cells (10) of each sub array (S1, S2, etc.) are simultaneously checked one row at a time and one column position at a time, to see whether or not any cell (10) is over-erased. If, at any time during the procedure a cell (10) is found to be over-erased, the over-erased condition is corrected and the erase procedure continues, but with erase pulses applied only to those subarrays (S1, S2, etc.) having non-erased memory cells (10) as in prior-art subarray erase procedures. Under almost all circumstances, the procedure of this invention decreases over-all erase time.
    Type: Grant
    Filed: June 12, 1996
    Date of Patent: June 3, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Tim M. Coffman, Sung-Wei Lin, Phat C. Truong
  • Patent number: 5604150
    Abstract: To ensure proper electrical insulation under thick-field isolation regions (23) grown in triple-well structures, the channel-stop impurity (30) is implanted using multiple doses at different energies, depending on the oxide thickness of the thick-field isolation regions (23). The split-implant procedure results in much wider process variation windows for the thick-field isolation regions (23). Process variations include oxide thickness of grown oxide, implant energy/dose and reduced thickness caused by wet de-glazing steps.
    Type: Grant
    Filed: October 25, 1995
    Date of Patent: February 18, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Freidoon Mehrad
  • Patent number: 5596528
    Abstract: The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction.
    Type: Grant
    Filed: September 22, 1995
    Date of Patent: January 21, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Cetin Kaya, Wayland B. Holland, Rabah Mezenner
  • Patent number: 5576992
    Abstract: An extended-life method for soft-programming at least one floating gate memory cell (10) includes connecting the substrate and the source (11) to a reference voltage, then applying to the control gate (13) a soft-programming voltage, the soft-programming voltage being between thirty and sixty percent of the voltage used to hard-program the cell. Increasing voltages are applied to the drain (12), while measuring the current flow into the drain (12). A specific drain (12) voltage, less than or equal to that value of drain (12) voltage at which the current flow into the drain (12) reaches a first peak, is chosen. With the substrate at reference voltage, the cell (10) is soft-programmed by applying to the drain (12) a first voltage slightly less than or equal to the specific drain (12) voltage; by applying to the source (11) a non-negative second voltage less than the specific drain (12) voltage; and by applying to the control gate (13) a third voltage no greater than the soft-programming voltage.
    Type: Grant
    Filed: August 30, 1995
    Date of Patent: November 19, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Freidoon Mehrad