Abstract: An extended-life method for soft-programming at least one floating gate memory cell (10) includes connecting the substrate and the source (11) to a reference voltage, then applying to the control gate (13) a soft-programming voltage, the soft-programming voltage being between thirty and sixty percent of the voltage used to hard-program the cell. Increasing voltages are applied to the drain (12), while measuring the current flow into the drain (12). A specific drain (12) voltage, less than or equal to that value of drain (12) voltage at which the current flow into the drain (12) reaches a first peak, is chosen. With the substrate at reference voltage, the cell (10) is soft-programmed by applying to the drain (12) a first voltage slightly less than or equal to the specific drain (12) voltage; by applying to the source (11) a non-negative second voltage less than the specific drain (12) voltage; and by applying to the control gate (13) a third voltage no greater than the soft-programming voltage.

Abstract: An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (21). Each memory cell includes a source region (11) and a drain region (12) formed in a shared drain-column line (19), with a corresponding channel region in between. A Fowler-Nordheim tunnel-window (13a) is located opposite the channel over the source-column line (17) connected to source (11). A floating-gate conductor (13) includes a channel section (29) and a tunnel-window section (28). The floating-gate conductor is formed in two stages, the first stage forming the channel section (29) and the tunnel-window section (28) from a first-level polysilicon. This floating-gate channel section (29) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (29).

Abstract: Sense amplifier circuitry (SC) includes a differential amplifier (A) having a reference input and a memory input. The output of a first sense amplifier (SA1) is coupled to the reference input of the differential amplifier (A) and to the input of a second sense amplifier (SA2). The output of the second sense amplifier (SA2) is coupled to the memory input of the differential amplifier (A) and to the input of the first sense amplifier (SA1). The first sense amplifier (SAR) and the second sense amplifier (SA2) include identical mirror transistor circuits (M1, M2, M3, M4).

Abstract: The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells (10). Each cell includes a control gate (14), a source (11) and a drain (12). The method comprises connecting the control gates (14) to a control-gate voltage (Vg), connecting the sources (11) to a source voltage (Vs) having a higher potential than the control-gate voltage (Vg) and connecting the drains (12) to a drain subcircuit (DS) having, in at least one embodiment, a potential (Vd) between the control-gate voltage (Vg) and the source voltage (Vs), the drain subcircuit (DS) having a sufficiently low impedance to allow current flow between the sources (11) and drains (12) at a time during the erasing operation. The drain subcircuit (DS) allows for optimum threshold voltage distribution and a part of the drain potential (Vd) may be fed back to arrest the erase process at an optimum point.

Abstract: An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region between. A Fowler-Nordheim tunnel-window (13a) is located over the source line (17) connected to source (11). A floating gate (13) includes a tunnel-window section. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch).

Abstract: An input protection device is presented for improving I/O electrostatic discharge ESD tolerance. The present invention protects a selected device by providing a sufficient potential difference between the substrate and the source of the device in question to protect it against an electrostatic discharge. In one embodiment of the invention, a resistor is placed between the substrate and the internal V.sub.SS connection. All V.sub.SS to substrate contacts have to be removed for internal V.sub.SS busses to be maintained at a predetermined resistance between the substrate and V.sub.SS. In other embodiments of the invention, an active device is placed between the substrate and the internal V.sub.SS connection. As with the first described embodiment, all V.sub.SS to substrate contacts have to be removed for internal V.sub.SS busses to be maintained at a predetermined resistance between the substrate and V.sub.SS. The active device presents a high impedance when not powered on and is very conductive when powered on.

Abstract: Memory cell transistors are provided in which column structures (12a, 14a) are formed at the face of a semiconductor substrate (10). Floating gates (46) and control gates (52) are formed adjacent to the column structures (12a, 14a). The floating gates (46) and control gates (52) are insulatively disposed by gate oxide layer (42) and insulating layer (50). Source regions (36) are implanted in the semiconductor substrate. Drain regions (38) are also implanted in the column structures (12a, 14a).

Abstract: In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allows application of a negative voltage of perhaps -8 V to the P-tank encasing the memory array. Application of that negative voltage permits the cells of the memory array to be programmed with voltage pulses having a peak value of about +10 V, rather than the +18 V peak value of prior-art memory arrays. Because the external circuitry, such as the wordline driver circuit, need drive the wordlines at +10 V rather than +18 V, the invention permits construction of that external circuitry using thinner gate insulators and space-saving shorter dimensions.

Abstract: A virtual ground memory includes an array of rows and columns of memory cells and a plurality of alternating first and second column lines. The cells in each column are coupled to a first column line and a second column line. A first decoder selects a plurality of first column lines in response to first decoded address signals and selects one of the selected plurality of first column lines in response to second decoded address signals.

Abstract: The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a micro-instruction decoder (MID), a test input multiplexer (TIM) to test control signals, an optional status output register (SOR) to generate control signals, and an optional subroutine stack (SS) to allow function calls. Complex program, erase, and compaction instructions for the integrated-circuit memory are implemented using a relatively small number of control-read-only-memory locations and using a relatively small surface area on the memory chip. Control instructions are easily modified to compensate for process and structure enhancements are made during the production lifetime of an integrated-circuit memory.

Abstract: A method for erasing blocks of a non-volatile memory includes detecting whether a block is in at least one of an erased state or a state secured from erasure; then setting a flag register at a first level for each block detected to be in at least one of an erased state or a state secured from erasure or at a second level for each block not so detected; then selecting for erasure blocks that have their respective flags set at the second level; and then erasing the selected blocks.

Abstract: A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.

Abstract: The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11 ) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction.

Abstract: A level shifter circuit 150 for selecting different voltage levels for programming memory cells 10 is provided. The level shifter 150 has an input 152 connected to a control circuitry and an output 154 connected to memory cells 10. The level shifter 150 is connected to two voltage sources: a high voltage source 166 and a low voltage source 164. The level shifter 150 has an isolation transistor 156 to buffer the input control circuitry from the higher voltage in the level shifter 150. Depending on the input control signal, either a first switching transistor 158 will select the low voltage source 164 for output or a second switching transistor 162 will select the high voltage source 166 for output. A pull-up transistor 162 is used to maintain the state of the switching transistors 158, 160 when the voltage sources 164, 166 ramp up. A voltage limiting transistor 170 reduces the voltage potential (breakdown voltage) across the drain and source terminals of the pull-up transistor 162.

Abstract: The power-on-reset test circuit of this invention includes two imbalanced latches to detect the occurrence of a transient power-on-reset signal. The occurrence of a transient power-on-reset signal is latched for later verification during circuit testing. Both latches are designed to default to a low voltage output (Vss) on initial power-up. One of the latches is set by the power-on-reset signal to a high-voltage output (Vcc) state. The other latch is set by a reference-potential input to a low-voltage output state. If the set latch has a high-voltage output and the other latch has a low-voltage output, then the power-on-reset circuitry is functioning properly.

Abstract: The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells (10). Each cell includes a control gate (14), a source (11 ) and a drain (12). The method comprises connecting the control gates (14) to a control-gate voltage (Vg), connecting the sources (11 ) to a source voltage (Vs) having a higher potential than the, control-gate voltage (Vg) and connecting the drains (12) to a drain subcircuit (DS) having, in at least one embodiment, a potential (Vd) between the control-gate voltage (Vg) and the source voltage (Vs), the drain subcircuit (DS) having a sufficiently low impedance to allow current flow between the sources (11) and drains (12) at a time during the erasing operation. The drain subcircuit (DS) allows for optimum threshold voltage distribution and a part of the drain potential (Vd) may be fed back to arrest the erase process at an optimum point.

Abstract: An array source signal discharge controller device (10) includes a pulse converter circuit (12) that receives an erase pulse signal (ERPULSE). The pulse converter circuit (12) converts the erase pulse signal (ERPULSE) into a pulse control signal (ERPCL) that is subsequently translated into a higher voltage level bias signal (ECL.sub.--). The higher voltage level bias signal (ECL.sub.--) drives array source signal generator circuits (16) that produce array source signals (AS) to erase particular array subsections of memory as determined by a selection circuit (17). The array source signal generator circuits (16) also generate array source command signals (ASCOM.sub.--) to indicate a discharging status of all array source signals (AS). An erase completion detector circuit (18) monitors the array source command signals (ASCOM.sub.--) and generates an array source detect signal (ASDET) to indicate completion of array source signal (AS) discharging.

Abstract: A system for erasing a memory array in a memory has a supply voltage and a negative charge pump. The negative charge pump system includes (a) circuitry to select a memory array to be erased; (b) for circuitry to switch on the supply voltage Vnn for the charge pump; (c) circuitry to pump the supply voltage Vnn with the charge pump to produce a pumped negative voltage; (d) circuitry to erase the selected array with the pumped negative voltage; (e) circuitry to provide the pumping; and (f) circuitry to provide a discharge path for voltages trapped in the charge pump.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.

Abstract: An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source (11) and a drain (12), with a corresponding channel (Ch) between. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the sources (11) and drains (12), such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). Each memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) to the source (11).