Abstract: A direct digital synthesis is provided with added circuitry to reduce jitter in an IC so that a programmable frequency output can be provided near the limits of the IC system clock with minimal jitter. The system derives the quotient Q as a remainder R in an accumulator at the instant of an overflow, divided by a programmable input N. The quotient Q is subjected to conversion logic that can be provided by a fast parallel to serial converter such as, for example a multi-gigabit transceiver (MGT) of an FPGA. As an alternative to an MGT, a series of delay devices such as found in a carry chain can be used if calibration is performed to assure the accuracy of delays.

Abstract: A plurality of programs are statistically multiplexed using a statistical multiplexing (stat mux) system. Rchannel, a constant total bit rate for the plurality of programs, is determined. Cl,Ff,picTYpe, a complexity for each picture in the plurality of programs, is determined. Tl,Ff,picType, a bit allocation for each picture in the plurality of programs, is determined based on Cl,Ff,picTYpe and Rchannel. The plurality of programs are encoded using a plurality of encoders, a combined encoder buffer, and Tl,Ff,picType to form a plurality of variable bit rate (VBR) compressed bit streams. The plurality of VBR compressed bit streams are multiplexed to form a single constant bit rate (CBR) bit stream.

Abstract: A method and system for embedding and recovering a spatial fingerprint in a sequence of video frames. The sequence includes marked frames that include marked groups having markable positions. The embedding method selects a frame offset and marking period for the marked frames, and determines a marking strength for modifying each marked group. A portion of the spatial fingerprint is embedded in each marked group of a first subgroup of the marked groups, and an ordering of the portion embedded in the first subgroup is embedded in each marked group of a second subgroup of the marked groups. The recovering method analyzes a quality ratio of the DCT transform energy and the residual for each markable position in the frame to determine whether the frame is a marked frame. The recovering method recovers the spatial fingerprint when the marked groups maintain the quality ratio in a number of successive marked frames.

Abstract: A system is configured to transcode a first MPEG stream to a second MPEG stream. The system includes a first MPEG decoder capable of decoding the first MPEG stream and a second MPEG encoder capable of producing the second MPEG stream. The second MPEG encoder is configured to maintain a decoded picture type of I, P, or B. The second MPEG encoder is also configured to maintain a decoded picture structure of frame or field, identify a metadata per each macroblock (MB) of an MB pair of the first MPEG stream, and determine whether to re-encode the MB into the second MPEG stream using one of a frame or a field mode based on the identified metadata. The second MPEG encoder is further configured to re-encode the MB pair into the second MPEG stream using one of the frame or the field mode based on the identified metadata.

Abstract: In a method for securing content in a system containing a security processor configured to control access to the content by a main processor, in which main processor being configured to send heartbeats to the security processor, a determination as to whether at least one heartbeat was received within a predicted time interval is made and in response to a determination that at least one heartbeat was not received with the predicted time interval, access to the content by the main processor is ceased.

Abstract: A suspend mode is provided that can be asserted using an Internal Configuration Access Port (ICAP) of an integrated circuit such as a Field Programmable Gate Array (FPGA), as supposed to a dedicated external suspend pin typically accessed by a device external to the FPGA. The ICAP is designed to assert the suspend mode through a configuration block to maintain the state of the configuration memory array while lowering power, in a similar manner to when an external suspend pin is accessed. Internal circuits can, thus, be used to assert a suspend mode through the ICAP.

Abstract: A serializer is provided to serialize combined synchronization information and data blocks for transmission over the high-speed channel. A gearbox combines synchronization information with data blocks to present to the serializer. A scrambler scrambles data blocks to present to the gearbox. An encoding device stores a program that contains instructions to format the data blocks for sending over the high-speed channel. The formatting reduces a number of operations used to receive the data blocks by a receiver.

Abstract: A First In First Out (FIFO) communication buffer for receiving data from a source and distributing the data to a first sink and a second sink is disclosed. The FIFO communication buffer includes a FIFO memory and a FIFO control circuit. The FIFO memory includes a first data port, a second data port, and a third data port. The FIFO control circuit provides the first address, the second address and the third address. The FIFO control circuit increments the first address toward the second address and the third address when valid data is received, and increments the second address and the third address when data is read out.

Abstract: A FIFO communication system is provided using a FIFO and connection circuit to transmit data from a single source to multiple sinks. The connection circuit operates to enable simultaneous reads by the multiple sinks with a single output port FIFO. Multiple FIFOs can likewise be used to distribute data from a single source to multiple sinks without requiring a simultaneous read by both sinks. Similarly, a multiple output port FIFO can be used to supply multiple sinks without requiring simultaneous reads and without requiring additional memory use.

Abstract: A circuit to generate Orthogonal Variable Spread Factor (OVSF) codes for CDMA systems. The circuit includes a shift register to determine the OVSF code k for a given spread factor SF, wherein k ranges between 0 and (SF?1). A memory cell register stores the leftmost bit of the code that is loaded into the first bit of the shift register. An XOR gate provides an input to the shift register after the first bit is loaded from the memory cell. An address Look Up Table (LUT), or state machine, is connected to the shift register to select a tap output from one of the shift register bits to provide a first input to the XOR gate. A secondary OVSF code register connects to a second input of the XOR gate to provide code bits from lower SF values making up the code from the current SF value.

Abstract: A Programmable Logic Device (PLD) is provided with configuration memory cells displaying a superior soft error immunity by combating single event upsets (SEUs) as the configuration memory cells are regularly refreshed from non-volatile storage depending on the rate SEUs may occur. Circuitry on the PLD uses a programmable timer to set a refresh rate for the configuration memory cells. Because an SEU which erases the state of a small sized memory cell due to collisions with cosmic particles may take some time to cause a functional failure, periodic refreshing will prevent the functional failure. The configuration cells can be DRAM cells which occupy significantly less space than the SRAM cells. Refresh circuitry typically provided for DRAM cells is reduced by using the programming circuitry of the PLD. Data in the configuration cells of the PLD are reloaded from either external or internal soft-error immune non-volatile memory.

Abstract: A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.

Abstract: A test setup is provided to test differential signals outputs from the I/O block (IOB) pairs in an integrated circuit (IC). The test setup allows elimination of the external 100 Ohm resistors provided across the differential outputs on a device under test (DUT) test board containing the IC by taking advantage of a 100 Ohm resistor built into the IC between a portion of the IOB pairs. An IOB pair being tested may have its differential output terminal pair shorted to the differential output terminal pair of the IOBs having the internal 100 Ohm resistor.

Abstract: Performance monitors (PMs) are provided in a system to identify the execution time for data being transferred within the system and determine operation parameters of the system based on the rate data is transferred. The operation parameters are then used to configure hardware within the system. The PMs can provide a histogram of the transactions usable to evaluate system performance. The PMs can provide a time line diagram of the transactions to show the specific order the transactions occurred. The PMs can be provided in a multi-port memory controller (MPMC) to monitor the speed of read and write transactions from the MPMC ports, and used to configure logic within the MPMC to maximize the rate of data flow.

Abstract: A state machine is provided with outputs that have programmable delays that enable the state machine to be compatible with a number of different devices. The state machine uses shift register look up tables (SRLs) to provide variable output delays. The state machine can be provided in the BRAM of an FPGA, and can be used to provide control logic in a multi-port memory controller (MPMC). The MPMC with such a state machine can then connect to multiple different types of memory devices either simultaneously or separately.

Abstract: A model and method are provided for lowering device jitter by controlling the stackup of PCB planes so as to minimize inductance between a FPGA and PCB voltage planes for critical core voltages within the FPGA. Furthermore, a model and method are provided for lowering jitter by controlling the stackup of package substrate planes so as to minimize inductance between a die and substrate voltage planes for critical core voltages within the die.

Abstract: A memory coupled to a programmable logic device (PLD) is configured through the PLD's JTAG port. A soft core loaded into the PLD connects to the JTAG port and memory. An external programming host device connects to the JTAG port, sends instructions and data to and receives data from the memory via the JTAG port and soft core. A synchronization JTAG instruction is loaded, and a Shift Data state of the JTAG port state machine is used. The programming host device and soft core are synchronized, and a memory chip select is asserted. A memory instruction, such as READ, WRITE or ERASE is loaded into the memory. An RTI state of the state machine is used to wait for instruction completion and the chip select is deasserted. Another instruction is processed starting with using the Shift Data state. Alternatively, a PLD Shift Data Register is used in conjunction with the soft core.

Abstract: A method is provided to automatically allocate resources of an integrated circuit (IC) to form multipliers in a given design to optimize the use of IC resources. Information about the multipliers in the design is extracted to place the multipliers into a priority order. The priority allows primitives in the IC, like DSP blocks LUTs or MUXCYs to be economically allocated to the multipliers. The ordering criteria can include: (1) a user defined criteria, (2) the number of primitives required to implement a multiplier, or (3) a size of the multiplier operands. This invention further optimally allocates LUTs and MUXCYs when DSP48 blocks are exhausted. The steps for generating a multiplier include: constructing a partial product matrix and minimizing the adders used in the multiplier by minimizing the size of support for the partial products. Either LUTs or MUXCYs are selected depending on the size of support determined.

Abstract: Apparatus and methods of testing for bridge faults in nets of the interconnect of a programmable integrated circuit. Each net is sourced by a function generator (e.g., a look up table) configured as a clocked shift register. For each net group, shift registers connecting nets in the group are initialized identically to one value and are initialized to a different unique value from shift registers connecting nets of other net groups. Each shift register stores one bit with a value one and zeros in all other bits. When the shift register is clocked, it provides a single one on one clock cycle and provides zeros in all other clock cycles. At the end of n clock cycles, where n is the length of the shift register, if the load on any net has a value that is different from the value provided by the net's corresponding shift register, a short is detected.

Abstract: Testing of routing resources in a path between network nodes is provided using simpler nodes to replace more complex IP modules which could be programmed into an FPGA after the routing resources are tested. Further, when it is impractical to generate a pattern from a source node S for testing a network path N to a load, subnetworks are created to perform testing. To provide the subnetworks, a source S? is first provided close to node S that generates signal patterns to route through a path N? to load L. When it is impractical to test a network path N from source to load L, a load L? is further provided close to load L that receives the signal patterns from a routing path N? provided from source S. The paths N? and N? overlap to cover all the routing resources of the path N.