Abstract: A protective mechanism for a probe card cover to prevent the probe card cover or attachment screws extending from the probe card cover from striking a wafer in a test system if the probe card is installed without removing the cover. The protective mechanism includes an elongate member that can be permanently attached to the probe card cover, or attached by screws to the probe card cover. The protective mechanism can be a bar that extends longer than an opening in a probe card holder tray through which probes of the probe card pass during testing. The bar can be hard, yet flexible enough to prevent damage to the probe card holder tray or probe card.

Abstract: A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.

Abstract: A clock manager circuit includes a number of clock output blocks, each providing an independent output. Counter controlled delay devices (CCDs) are used in these clock output blocks. To achieve full cycle delays, the CCDs are placed in parallel with outputs of the CCD outputs driving set and reset terminals of a common latch. The parallel connection of the CCDs, as opposed to a series connection, offers an increase in maximum frequency and possibly fewer needed CCDs than if the CCDs are placed in series. In one embodiment, at least one of the CCDs includes a counter/compare circuit with a frequency divider enabling the frequency of the CCD to be varied relative to the common input clock.

Abstract: A Direct Memory Access (DMA) system is provided for simplified communication between a processor and IP cores in an FPGA. The DMA system includes use of dual-port BRAM as a buffer and a decoder as a DMA control signal identification mechanism. The DMA control signals are stored in an area of the BRAM memory recognized by the decoder using chip enable (CE), write enable (WE), and address (ADR) signals. The decoder, upon recognizing a DMA control signal, will generate an event vector. The event vector triggers a READ operation by the receiving device at the associated BRAM control data memory address. DMA control codes can be detected as sent from either the processor or the IP core or both, depending upon whether the system employs a MASTER/SLAVE, SLAVE/MASTER, or PEER/PEER control model.

Abstract: Data is recovered in an asynchronous environment where a sampling clock is generated internally, and is not externally frequency locked, by using programmable delay modules each providing a number of delay tap outputs. To recover data, two of the delay modules are used with a first delay module designated as a monitor delay module to monitor the clock edge transitions, while a second delay module is designated as a data delay module that provides a data output. A controller provides for incrementing or decrementing the tap delay of both delay modules to assure clock data falls at the center of the monitoring window as determined using the monitor delay module. The controller further selects between the two delay modules as to which provides data and which is used as for clock edge monitoring when the clock edge transitions drifts to an edge of the monitoring window.

Abstract: A graphical user interface (GUI) is provided with a specifiable edit control field that is accessed in conjunction with a non-edit field, the non-edit field for example being a check box, or radio buttons. The specifiable edit field can be accessed for example by right clicking or double clicking on the non-edit field or overall GUI. The specifiable edit field allows changing parameters of the non-edit field via entry of a programmatic expression that evaluates to an valid input to the non-edit field. For example in a high-level modeling program that enables modeling modules of a Field Programmable Gate Array (FPGA), when a normal editing field can modify only one module at a time, the specifiable editing field can allow modifying a plurality of modules at one time that are hierarchically linked together by the associated non-edit field, such as a check box.

Abstract: A method for generating a design for an FPGA provides for partial reconfiguration by allowing relocation of the same single bitstream within different areas of the FPGA, reducing overall design time and PROM storage space needed for the design. The design rules for the method include a requirement that the same frames oriented in the same relative location be available in dynamic areas where a bit stream will be located. Further, the rules require the same relative communication interfaces be available between the dynamic areas and static areas when the bit stream is relocated. Additionally the design rules require global resources, such as clock resources used by the static areas remain the same when the bit stream is relocated.

Abstract: A low jitter digital frequency synthesizer includes a first counter module, a second counter module, a snapshot module, an error value generation module, and a tapped delay line. The first counter module counts intervals of M cycles of an input clock to produce a first count. The second counter module count intervals of D cycles of an output clock to produce a second count, wherein an average rate of the output clock corresponds to M/D times a rate of the input clock. The snapshot module periodically takes a snapshot of the first and second counts to produce snapshots. The error value generation module generates a modulated error value based on the snapshots and a modulation value, where the modulation value is used to spread the spectrum of the output clock. The tapped delay line module produces the output clock based on the modulated error value.

Abstract: An eFuse sensing circuit replaces the inverters used to provide the “read” output state of a conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The reference voltage generator circuit includes an internal resistor. Transistors of the sense circuit are provided to mimic the transistors of the eFuse circuit, so that variations of transistors due to process, voltage and temperature will be substantially the same. The resistor of the sense circuit is then effectively compared with the resistance of the eFuse by the comparator irrespective of temperature and process variations.

Abstract: A crossbar switch is implemented in a reconfigurable circuit, such as a FPGA, instantiated with a number of modules, the crossbar switch providing communication links between the modules. The modules and crossbar switch can be easily updated in a partial reconfiguration process changing only portions of modules and the crossbar switch while other portions remain active. The crossbar switch uses individual wiring to independently connect module outputs and inputs so that asynchronous communications can be used. The crossbar switch can be implemented in different embodiments including a Clos crossbar switch, and a crossbar switch connecting each module output only to a corresponding module input, allowing for a reduction in the amount of FPGA resources required to create the crossbar switches.

Abstract: An FPGA system includes a combined shift register and look up table (LUT) forming a shift register LUT (SRL) that provides data write, reset and shift enable on a cell-by-cell basis. The data write and reset can be performed during FPGA operation without requiring a number of frames or columns of configuration memory cells to be reprogrammed, as with conventional SRAM cells. The shift enable provides for synchronization to facilitate the cell-by-cell write and reset.

Abstract: A method is provided to program a memory device through a JTAG interface of an attached component with programmable logic, wherein the memory device does not have a JTAG interface. Initially, programming hardware to provide for programming of the attached memory is downloaded into the component via the component's JTAG interface. The programmed component then becomes a serial data link between the JTAG port attached to a host programmer and a non-JTAG port attached to the memory device. The circuitry downloaded or programmed into the component controls the timing and the protocol to program the external memory.

Abstract: An architecture for a Block RAM (BRAM) based arbiter is provided to enable a programmable logic device (PLD) to efficiently form a memory controller, or other device requiring arbitration. The PLD arbiter provides low latency with a high clock frequency, even when implementing complex arbitration, by using BRAM to minimize PLD resources required. The architecture allows multiple complex arbitration algorithms to be used by allowing the multiple algorithms to be stored in BRAM. With multiple algorithms, dynamic configurability of the arbitration can be provided without halting the arbiter by simply changing an algorithm stored in BRAM. Additionally, algorithms can by dynamically modified by writing to the BRAM. With BRAM memory used for arbitration, PLD resources that would otherwise be wasted are frees up to be used by other components of the system.

Abstract: A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.

Abstract: DC balance is obtained in an integrated circuit (IC) having I/O pins with AC coupling by effectively bypassing the AC coupling. The DC balance is accomplished by mixing in a known, low frequency mix signal or carrier in a circuit external to the IC and then digitally canceling out that mix signal inside the IC fabric. The mixer or modulating circuitry external to the IC can be a simple XOR gate. With the IC being an FPGA, the logic internal to the FPGA can be programmed to form the demultiplexing circuitry to digitally cancel out the mix signal, as well as to provide a carrier signal to the external mixer. To minimize errors due to data signal transitions near the edge of the carrier signal, a cleaner circuit is used to eliminate transitioning bits on either side of a carrier signal edge. With modulation used, synchronization circuitry is likewise included to provide synchronization during startup as well as after long dead times in the data signal.

Abstract: A Programmable Logic Device (PLD), such as a Field Programmable Gate Array (FPGA), is provided with components of a Radio Frequency Identification (RFID) tag and circuitry to enhance operation. The RFID antenna and circuitry is provided in either directly in layers of the die forming the PLD, on a die package containing the PLD die, or on a printed circuit board containing the PLD. An RFID antenna provides a source of power from an external electromagnetic radiation source (such as an RFID reader) during storage of the PLD to prevent loss of decryption software in volatile memory should batteries run down. The RFID antenna can further provide a path for providing a bitstream to program the PLD as well as to read data to verify programming. With multiple PLDs having RFID antennas, programming of the PLDs can be performed in parallel. Further, the RFID antenna can be used with limited PLD resources to identify the PLD for inventory.

Abstract: An FPGA design system includes the use of constraints in order to determine whether to associate arbitration logic with a bus or in slave modules. In one embodiment, area constraints can be used to determine whether a smaller design using arbitration logic at the bus should be used. In one embodiment, a latency constraint is used to determine whether a lower latency design with arbitration logic at the slave modules is to be used. In one embodiment, throughput constraints are used to determine whether a higher throughput design with arbitration logic at the slave modules is to be used.

Abstract: Multiple configurations are provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA), when connected to a serial peripheral interface programmable read only memory (SPI PROM) by using a programmable SPI address register incorporated into a SPI state machine of the PLD. A read command followed by a first address corresponding to first configuration data is sent from the SPI address register of the SPI state machine of the PLD to the SPI PROM. Data starting at the first address in the SPI PROM is then read by the PLD from the SPI PROM along with a second address corresponding to second configuration data. The first configuration data is stored in the PLD memory, and the second address is stored in the SPI address register. These steps may be repeated for subsequent boots of the PLD for additional configurations of the PLD.

Abstract: A built in self test (BIST) circuit is provided for a programmable logic device (PLD) constructed from fixed or hard core logic that includes circuitry to write recurring patterns of bits in the configuration memory in a frame by frame manner and read the cell state to enable the validation of every configuration bit at power up. The BIST circuitry can further be used to program the recurring patterns into the configuration memory, and then read frames of the configuration memory to detect the occurrence of single event upsets (SEU) that corrupt data in the configuration memory. The recurring patterns programmed do not require time consuming functional configuration of the PLD, and can be done in a production environment after power up without knowledge of how the PLD will later be configured. No soft logic is needed to form the BIST circuit, enabling 100% test coverage of the programmable configuration memory cells.

Abstract: A test system configuration is provided to enable testing of integrated circuit (IC) packages. The test system includes a test controller, an interface apparatus including a PC board with lines connecting the test controller to contact areas for contacting the IC packages and a handler for supporting the IC chips and interface apparatus to maintain electrical connections during testing. The handler includes docking plates for attaching to the PC board to provide a guide for the IC packages that are inserted in openings of the docking plates to align contacts of the IC packages and PC board. The docking plates are configured to provide quad (four) and octal (eight) test sites, with either the quad or octal docking plate mating to the same PC board and being supported in the same handler system. An alignment frame for mounting either the quad or octal docking plate is further provided as part of the handler.