Abstract: The present invention provides shunt voltage regulation by employing a rectifying means to rectify an incoming signal and a current sinking means to divert current from the output of the rectifying means in such a way that the output voltage is maintained at an appropriate level and the modulation level does not rise above the acceptable range. This is accomplished by having two feedback mechanisms for the control of said current sinking means. A first feedback mechanism utilizes a voltage dividing means to generate a control voltage signal that will cause the average output voltage of the rectifying means to be equal to the a reference voltage. A second feedback mechanism utilizes non-linear processing means and capacitors to transmit part of the modulation frequency to the control of the current sinking means, thereby keeping the modulation at the output of the rectifying mean at an appropriate level at all time.

Abstract: One embodiment provides an ankle-foot orthosis (32) for resisting plantarflexion of a patient's foot, the orthosis (32) comprising: a resiliently flexible sock-like structure (34) enveloping, in use, at least a portion of a patient's lower leg in the vicinity of the ankle and at least a portion of the plantar (46) and dorsal (48) aspects of the patient's foot. Another embodiment provides an ankle-foot orthosis (1) for resisting plantarflexion of a patient's foot, the orthosis (1) comprising: a resilient rib (3) locatable, in use, along and in abutment with at least a portion of the dorsal aspect of the patient's foot and at least a portion of the patient's lower leg, the orthosis (1) comprising means (7) for securing the rib (3) to the patient's foot and lower leg.

Abstract: A system and method for filling balloons. A reusable web holding uninflated balloons attached at the neck is loaded onto a machine for inflating balloons. This machine features a digital motion control apparatus which advances the web a precise distance. After the web advances, a supply nozzle is inserted into the neck of the uninflated balloon directly beneath the nozzle. The balloon is filled, the supply nozzle lifted, and the balloon is removed from the machine. The web is then advanced again and another balloon is filled.

Abstract: A drive for a wheelchair having two larger diameter drive wheels with axles, the drive with regard to each drive wheel, including inner and outer disks flanking the drive wheel and being in fixed rotational relation with the drive wheel about the axle, a lever having a lever axis, the lever rotatable about the axle and about the lever axis, a cam selectively rotatable about the lever axis by the lever to and from a contact position and a non-contact position with respect to the outer disk, and a shoe positioned for contact engagement with the inner disk when the cam is in the first position. When the lever is rotated about the axle, and the cam is in the contact position, the cam and the shoe frictionally engage the respective disks propelling the wheelchair.

Abstract: An EEPROM memory circuit in which the loading of the column latches can be performed simultaneously with reading of the memory array. In this memory circuit, the data input connects directly to the column latches, leaving the bit lines open for memory reading by the sense amplifiers, which is connected directly to the bit lines. Two separate Y address decoders, one feeding into the column latches and the other into the bit line select circuit, provide column latch and bit line selection respectively.

Abstract: An apparatus and method for concentrating and measuring low levels of cells in biological samples. The apparatus, or concentration device, consists of two chambers with an optically level collection membrane intermediating between the chambers. The collection membrane filters the biological sample, trapping cellular elements of interest. A vacuum may be attached to the device to assist in filtration. The surface area of the collection membrane matches the view field of a standard imaging system and the device can be mounted on a standard microscope stage. All the cells in the sample volume are collected onto the membrane. The view field provides a fixed volumetric area for cell counting. Since the volume of sample tested is known, the total number of cells in the original sample may be calculated. The sample reservoir of the concentration device may also be used for sample preparation.

Abstract: Disclosed is a self-aligned non-volatile memory cell including a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

Abstract: A method for imaging a fingerprint on an optical memory card having an upper transparent cover, a base and optical medium therebetween, wherein a cardholder imprints a fingerprint having a pattern of ridges and valleys on the upper cover of the card and a laser beam is scanned over the fingerprint. The laser beam is selectively transmitted by the fingerprint. The laser beam burns pits into optical medium areas corresponding to valleys of the fingerprint and is prevented from burning pits into optical medium areas corresponding to the ridges, thus producing a fingerprint image comprising light and dark areas in the optical medium corresponding to the pattern of ridges and valleys of the user's fingerprint.

Abstract: An error checking circuit that performs RS encoding and decoding operations and also generates CRC codes includes a configurable two-stage combinatorial circuit that carries out selected finite-field arithmetic operations associated with RS and CRC coding. Input registers store the generator polynomial and operand coefficients associated with the data blocks or packets being encoded or decoded, and an output register holds the intermediate working result and at the end the final result of the finite-field arithmetic operation. Each stage of the combinatorial circuit includes sets of AND and XOR gates performing bitwise finite-field multiply and add on the operand bits, and the connections between registers and gates and between gates in the two stages are configured by multiplexer units responsive to RS and CRC instructions. The two-stage combinatorial block can be replicated into a 4-stage or 8-stage arithmetic circuit for CRC mode.

Abstract: A multi-level non-volatile memory transistor is formed in a semiconductor substrate. A conductive polysilicon control gate having opposed sidewalls is insulatively spaced just above the substrate. Conductive polysilicon spacers are separated from the opposed sidewalls by thin tunnel oxide. Source and drain implants are beneath or slightly outboard of the spacers. Insulative material is placed over the structure with a hole cut above the control gate for contact by a gate electrode connected to, or part of, a conductive word line. Auxillary low voltage transistors which may be made at the same time as the formation of the memory transistor apply opposite phase clock pulses to source and drain electrodes so that first one side of the memory transistor may be written to, or read, then the other side.

Abstract: A modular multi-axis robot that can be configured to operate with two, three, four, five or six axes of movement and in various combinations of rotational and translational motion. The modules that make up the robot are fully detachable, interchangeable and are functionally independent with respect to each other. This allows the robotic apparatus to provide a flexible and custom solution for many different applications.

Abstract: A method for fabricating a shallow trench isolation structure is described, in which a bottom pad oxide layer, a middle silicon nitride layer, a middle oxide layer and a top silicon nitride layer are sequentially formed on a silicon substrate. Photolithographic masking and anisotropic etching are then conducted to form a trench in the substrate. An oxide material is then deposited on top of the top silicon nitride layer, filling up the trenches at the same time. A chemical mechanical polishing step is then employed to remove the oxide material by using the top silicon nitride layer as a barrier layer. The top silicon nitride layer is then removed, followed by an isotropic etch of the oxide layer below. With the middle nitride layer acting as a natural etch stop, the oxide material is sculpted to a desirable shape. The middle nitride layer and the pad oxide layer are subsequently removed to complete the fabrication of a shallow trench isolation structure.

Abstract: A power-on management system for an on-chip voltage down-converter, monitoring both external and internal voltage supplies to independently determine when both supplies have reached minimum levels for proper operation of on-chip circuitry. The power-on management system supplies output signals that: control the discharge of the internal supply nodes at the initiation of power-on; force the active mode of the voltage down-converter; and deactivate a fast local voltage reference on completion of power-on.

Abstract: A system for managing power cell information resources of a non-petroleum fueled vehicle, particularly electric or fuel cell vehicles of a fleet of vehicles. Such vehicles have power pack instrumentation for wirelessly reporting data to a base station computer including power pack charge parameters and GPS location in real-time. This data is applied to a database which documents past vehicle performance as well as contains minimal acceptable vehicle parameters. A prediction is made regarding remaining range, state of charge and vehicle scheduling, considering vehicle load or mileage efficiency and GPS location of the vehicle for appropriate dispatch.

Abstract: An EEPROM device constructed in a first active area having a multi-element floating gate structure, including a central polysilicon body surrounded by a polysilicon spacer element and mutually separated by an upright layer of thin oxide for electron tunneling. An auxiliary active area, isolated from the first active area, is employed as a charge reservoir for programming and linked to the first active area by an extended ion implantation region. Before the poly spacer is built, the central poly body is used as an alignment mask for source and drain implants. After implanting source and drain, the thin oxide is deposited and the poly spacer is built. A poly cap makes contact with the poly spacer but not the central poly body. A hole is made through the poly cap into the central poly body and then filled with metal, electrically joining the poly cap and the connected poly spacer with the central poly body so that the multi-element floating gate structure is at the same electrical potential.

Abstract: A system for cooling a structure exposed to solar radiation. The system includes a polymeric sheet covering one or more exterior surfaces of the structure. A water dispensing means associated with the sheet provides a flow of water across the sheet to wet the sheet, allowing evaporative cooling to take place. The color and construction of the sheet also provide for insulation against ambient heat and reflection of some solar energy. A sensor detecting an environmental condition, such as roof temperature or sheet wetting, may activate water flow by actuating a valve.

Abstract: A switch controlling circuit for the testing and fine-tuning of integrated circuits comprising of a series of flip-flops chain together in a serial manner. The contents of the flip-flop are shift in from the input of the first flip-flop in the chain. The output of each flip-flop connects to individual switch whereby the states of the flip-flops control the state of the switches.

Abstract: A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit, a settable latch, a signal path with inverter, and an output logic gate. The single path is coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) which includes an array of word lines and bit lines arranged in rows and columns for addressing, an array of OR gates, and a plurality of output logic circuits.

Abstract: Disclosed is a bus arbitration system and method which assume that each operation using the bus requires from one to five bus clock cycles. Each potential bus master has a dedicated bus request line and a dedicated bus grant line, both of which are connected to a centralized bus arbiter in the bus arbitration system of the present invention. When a potential bus master wants to use the bus for, for instance, three bus clock cycles, the bus master activates its dedicated bus request line for the same number of bus clock cycles as it would need of bus use (i.e. three bus clock cycles). This three clock wide bus request pulse is recorded in a bus request recording circuit in the centralized bus arbiter. Access to the bus can be granted by the centralized bus arbiter to a winning bus master under any bus arbitration policies.

Abstract: A flash memory with a page erase architecture using a local decoding scheme instead of the global decoding scheme known in the prior art. Under the local decoding scheme, the flash memory is partitioned into sections. Each section comprises a plurality of local decoder and local circuitry. The local circuitry comprises switches controlled by the global decoders and these switches switch only in erase operation and not read operation. The reading time is not affected. Each local decoder is coupled to each row of the memory array. Each local decoder comprises a PMOS transistor for passing negative voltages and two NMOS transistors for passing positive voltages so that a page erase is achieved and unselected rows can be protected from unwanted erasure without additional and complex circuitry. The global decoder is located outside of the sectors and provides global signals to all sectors via the local circuitry, thus saving area.