Abstract: An apparatus and method in which illumination light and collected emitted light share a pathway and subsequently are physically separated. The optical configuration is designed such that at the point of separation, the illumination light is at has a smaller cross sectional area than the collected light. Collected light is directed away from the pathway of the illumination light and to detection optics. This configuration is adaptable to illumination and light collection across a broad wavelength spectrum. This configuration is adaptable to scanning in a limited depth of field to allow high throughput optical analysis of samples.

Abstract: A power-on reset (POR) circuit comprises a transistor connected ad diodes for setting temperature time delay coupled to a power supply voltage, a transistor switch, and buffering circuits. The trip point voltage of the POR circuit depends only on one type of transistor, such as the switching transistor so that the p-to-n skew variations do not affect the trip point. The switching transistor has a resistor connected from base to ground and another resistor connected to the power supply voltage to limit current flow during transitions.

Abstract: A digital system having a split transaction memory access. The digital system can access data from a system memory through a read buffer (FIFO) located between the processor of the digital system and the system bus. The read buffer is implemented with two FIFOs, a first incoming data FIFO for reading data, and a second outgoing address FIFO for transmitting read requests. The processor of the digital system can access the data FIFO and read data while the data transfer is still in progress. This decreases the processing latency, which allows the processor to be free to perform additional tasks.

Abstract: A wireless transceiver featuring a compensating filter circuit with a frequency and optionally an amplitude response which has the same function as the composite of filter effects from the transmit side as well as from the intermediate frequency (IF) stage of the receive side. The compensating filtering approximately duplicates the effects of the phase lock loop on the transmit side and the effects of IF filtering on the receive side, as well as amplitude distortion in the detector, which would delay or distort the audio. Then, the compensated audio is added or subtracted, depending on phase considerations, from the receive signal so that the receive signal is free of filter artifacts.

Abstract: A variable charge pump circuit uses a plurality of selectable loads to minimize the voltage ripples of the pumped output by selecting the appropriate load for a preselected pump voltage. The charge pump circuit also compares the pump voltage to a reference voltage to shut down the variable charge pump circuit if the pump voltage is larger than the reference voltage. The charge pump circuit also compares the maximum voltage output to the reference voltage to monitor whether the maximum ripple on voltage output is larger than the reference voltage. The charge pump circuit comprises one or more stages operable to receive a supply voltage and generate one or more pump voltages, a plurality of loads each associated with a specific pump voltage, and a load selector means coupled to the output pump and the plurality of loads for selecting a load associated with a specific pump voltage.

Abstract: A paint roller having modular, rebuildable sections including a hollow tubular handle terminating in a cylindrical end connected to an offset midsection and a roller spindle rod. The offset midsection includes a pair of clamps at opposed ends. The first clamp includes a clamp body with a slotted opening and a collar having an opening within which said cylindrical end is received. A screw passing through the clamp body and collar is turned to retract the collar into the slotted opening thus locking the handle to the midsection. A second clamp includes a clamp housing with a threadable opening, a plastic bushing transverse to the threadable opening and a spindle rod having ridges passing through the plastic bushing. A set screw is insertable within the threadable opening, pushing a plastic surface of the plastic bushing into the ridges and locking the spindle rod to the clamp and attached midsection.

Abstract: A method of recovering overerased bits in a memory cell. In the method, a pair of reference currents are internally generated to define a current window corresponding to the erased state of the memory cell. The first reference current defines the highest current of the current window and the second reference current defines the lowest current of the current window. Then, it is determined which of the memory cells in a memory array are in an overerased state by having an amount of charge on its floating gate that corresponds to a conduction current during a read operation that is greater than the first reference current. Then, the overerased cells are programmed until the cells are in the erased state.

Abstract: A switch (1) comprising an outer housing (3) and an inner component (5); switch means (13) operable to provide a signal upon depression of said outer housing (3) resilient biasing means (29) located between the inner component and the outer housing to provide a force which bias the outer housing from the inner component; and means (9, 17) for varying the spacing between the inner component and the outer housing and hence the biasing force provided by said resilient biasing means.

Abstract: A computer program provides fast generation and testing of probable prime numbers for cryptographic applications. The program instructions executed on computer hardware execute steps that include a smart increment program function that finds successive candidates using a table of congruent values that are relatively prime to a selected set of very small primes do identify an increment to the next candidate, thereby sieving out about ¾ths of the really obvious components that don't need to be subjected to trial division. The program instructions also include a small primes testing program function that speeds trial division against a list of small primes by carrying out the division on modular reduced values rather than the very large candidates themselves. Only the about 10% of the candidates that pass the small primes test will then be subjected to more rigorous, but time consuming, probable primality tests.

Abstract: A method of programming a multi-level memory chip in which the first, or lowest, voltage memory state through the next-to-last voltage memory state are programmed by a plurality of programming pulses increasing incrementally in voltage, alternated with a plurality of verify pulses, and in which the last, or highest, voltage memory state of the memory cell is programmed with a programming pulse of the threshold voltage required for charging the memory cell to the highest voltage memory state. The programming method provides accuracy in programming the intermediate memory states of the cell, while providing speed in programming the last memory state of the cell to increase the overall speed of the programming the memory cell.

Abstract: A system and method for finding available memory space associated with an inactive memory transfer controller and activating the inactive memory transfer controller using indexed addressing. A memory transfer engine includes a plurality of memory transfer controllers, each configured to move data from a source address to a destination address. An active memory transfer controller can execute an instruction to find an inactive memory transfer controller associated with available memory space. The inactive memory transfer controller is activated by writing to its hardware registers, thereby assigning it a task, using indexed addressing.

Abstract: A method for fabricating a silicon dioxide/silicon nitride/silicon dioxide (ONO) stacked composite having a thin silicon nitride layer for providing a high capacitance interpoly dielectric structure. In the formation of the ONO composite, a bottom silicon dioxide layer is formed on a substrate such as polysilicon. A silicon nitride layer is formed on the silicon dioxide layer and is thinned by oxidation. The oxidation of the silicon nitride film consumes some of the silicon nitride by a reaction that produces a silicon dioxide layer. This silicon dioxide layer is removed with a hydrofluoric acid dilution. The silicon nitride layer is again thinned by re-oxidization as a top silicon dioxide layer is formed on the silicon nitride layer. A second layer of polysilicon is deposited over the silicon nitride, forming an interpoly dielectric.

Abstract: A low current detector using magnetoresistive sensor is used in a ground fault detector that opens a current carrying circuit when an unbalanced or dangerous condition occurs in the circuit. The current circuit has windings wrapped around a toroidal member of magnetic material having a cross sectional gap. First magnetic flux lines induced in the toroidal member by the circuit project from the gap toward a permanent magnet having second emergent magnetic flux lines that bend the first flux lines in a flux line mesh zone when an unbalanced current exists in the current carrying circuit. The flux lines are non-existent in the gap of the toroidal member when the circuit is in a balanced or non-fault state. A magnetoresistive sensor is disposed in the mesh zone in a position producing a signal indicative of an unbalanced condition caused by a current fault. A circuit breaker, connected to flux sensor responds to the signal indicating an unbalanced condition by opening the circuit.

Abstract: Methods for waking up an idle memory transfer controller (MTC) in response to an event from an external source. The first mechanism, Parameter List Pointer (PLP) FIFO Wake Up, wakes up an MTC after an external agent writes to an MTC's PLP FIFO. This activates the MTC's run bit, making the MTC eligible to execute instructions if chosen to do so by the memory transfer engine arbiter. This mechanism allows the MTC to distinguish between multiple possible originators of multiple possible wake-up events; wake-up events may be queued. Events may be directed to particular MTCs or to the next MTC available to process the event. The second mechanism wakes up an MTC after an external agent writes to an MTC's external wake-up address. This sets the MTC's run bit, making the MTC eligible to execute instructions if chosen to do so by the memory transfer engine arbiter. This approach only recognizes one event and one source. Events may not be queued using this approach.

Abstract: A sense amplifier that is configurable to operate in two modes in order to control a voltage swing on the sense amplifier output. The sense amplifier has two feedback paths including a first feedback path having a transistor with a fast response time in order to allow the circuit to operate as fast as possible, and a second feedback path for providing voltage swing control. In the first operating mode, the “turbo” mode, both feedback paths are in operation to provide a higher margin of swing control, thus higher sensing speed. In the second operating mode, the “non-turbo” mode, only the first feedback path is in operation which allows for greater stability and a reduction in power consumption.

Abstract: An integrated multi-processor system with clusters of processors on a high speed split transaction bus uses a transaction acknowledge (TACK), by a target device in response to receiving a request from a master device on the bus. The master and target devices connect to the bus via a global bus interface with FIFO registers acting as buffers, and the target interface includes a TACK generator that flips the state of the global bus' TACK line upon determining that a broadcast request is addressed to its target device. A bus idle default device (BIDD) generates a TACK signal when no device is on the bus, and also detects the absence of any TACK response by monitoring the state of the TACK line, thereby indicating that a master device bus attempted to address a nonexistent target a device. The BIDD then generates a dummy response for the requesting master device with data flags set to invalid data.

Abstract: A continuity test mode circuit in an integrated circuit device having a means for switching between a continuity test mode and a normal operating mode. The test mode is characterized by one or more input pins being in direct electrical connection with one or more output pins to enable the pins and the chip packaging and chip socket and circuit board to be tested for continuity. In normal operating mode, the operation of the chip is not affected by the test mode circuitry. The continuity test mode circuit allows for testing of device-socket and/or device-board continuity in order to ensure accurate testing and programming of the device.

Abstract: Chemically specific fiber and waveguide sensors are formed in a fiber optic or optical waveguide material in which injected light is trapped within a Bragg grating optical cavity. The Bragg cavity effectively traps the light for long times, corresponding to effective path lengths equal to hundreds or thousands of meters in the fiber or waveguide medium. The Bragg grating optical cavity is surrounded by a cladding of chemically sensitive material whose optical properties change when exposed to specific chemicals or classes of chemicals. The change in the optical properties of the cladding results in a change in the light trapping characteristics of the fiber or waveguide. Changes in optical transmission of the fiber optic or waveguide sensor can then be related to the concentration of specific chemicals or classes of chemicals in the environment surrounding the sensor.

Abstract: A MOS transistor having utility as a charge storage device, as in a nonvolatile memory device, or as an amplifier, using the charge storage feature of the device as a way to modulate the conductivity of a channel between source and drain electrodes. Over a doped substrate, a gate oxide layer isolates a doped, electrically isolated, charge reservoir layer from the substrate. An overlying tunnel barrier layer isolates the charge reservoir layer from a nanocrystal layer capable of receiving or dispensing electric charge to the charge reservoir layer under the influence of a control gate overlying the nanocrystal layer and separated by an oxide layer. Electric charge on the charge reservoir layer influences the conductivity of the channel. The device may be operated in a memory mode, like an EEPROM, or in an amplifier mode where changes in the gate voltage are reflected in conductivity changes of the channel.

Abstract: A solid-waste conversion plant produces useful products and electrical energy in a closed system with zero emission of pollutants into the atmosphere. The plant is characterized by catalytic ionic-impact chambers having a pair of electrodes that establish an electric arc. The electric arc breaks down solid waste molecules into a plasma of atomic constituents which exothermically recombine into simple molecules upon leaving the plasma. A primary chamber converts carbon-based waste into solidifiable metal, sulfur and glassy slag extractable from the bottom of the chamber, and into gas containing CO, H2, and CH4. A second chamber contains high carbon waste input that is converted by the arc into incandescent coke, which converts CO2 and H2O in the gas from the first chamber into more CO, H2 and CH4, thereby forming a fuel gas. The fuel gas is combusted in gas turbine generators to produce electricity for operating the electric arcs, plus a sellable surplus.