Patents Represented by Attorney Thomas Schneck
  • Patent number: 6618297
    Abstract: In order to establish boundary current levels for more than two memory states, a circuit is provided that uses reference currents defining the center of each state. The reference currents are defined by multiple pre-programmed reference memory cells or by a single reference memory cell together with a current mirror that sets the other reference currents at specified proportions of a first reference current. With these reference currents, an analog circuit block generates fractional currents at (1−m) and m of the reference currents, where m is a specified margin value equal to 50% for read operations and less than 50% for program verify operations, then combines fractional currents for adjacent states to produce the boundary current levels. The fractional currents may be obtained with pairs of current mirrors biased by sense amplifiers for the various reference currents.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: September 9, 2003
    Assignee: Atmel Corporation
    Inventor: Danut I. Manea
  • Patent number: 6618289
    Abstract: A bit/column latch comprising a pair of first and second cross-coupled CMOS inverters. Each inverter of the pair comprises an NMOS transistor and a PMOS transistor. The first CMOS inverter has the source of its NMOS transistor coupled to ground via a control transistor and has its output connected to the associated bit line. When low voltage data intended for the associated memory cell appears on the bit line, the control transistor is barely turned on to weaken the NMOS transistor of the first inverter. This makes it easier for the data on the bit line to turn on the NMOS transistor of the second inverter so as to switch the bit latch from storing a ‘low’ to storing a ‘high’. In other words, the data bit from the bit line is loaded into the bit latch. After that, the control transistor is strongly turned on and therefore it becomes transparent to the latch. As a result, the latch is stable when the bit line later ramps up to a high programming level.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: September 9, 2003
    Assignee: Atmel Corporation
    Inventors: Saroj Pathak, James E. Payne, Harry H. Kuo
  • Patent number: 6608787
    Abstract: A single-ended sense amplifier having a precharge circuit for maintaining a stable voltage on a bitline, a sensing circuit coupled to the bitline for sensing an amount of current flowing into the bitline, a direct current amplification circuit electrically coupled to the sensing circuit for amplifying the current sensed on the bitline, a current-to-voltage conversion circuit for converting the sensed current to a voltage and a voltage amplification circuit for amplifying the voltage at the sense amp output. The sense amplifier can be implemented using standard CMOS components and provides improved access time at low power supply voltage, high robustness to process variations, and the ability to sense very low currents.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: August 19, 2003
    Assignee: Atmel Corporation
    Inventors: Jean Michel Daga, Caroline Papaix, Jeanine Guichaoua
  • Patent number: 6600789
    Abstract: The invention relates to digital signal processing and specifically to level control of a pulse density modulated (PDM) signal generated by a sigma-delta modulator. A single-bit pulse density modulated PDM signal is generated by a first sigma-delta modulator being an analog modulator, for instance. Level control is performed by multiplying the single-bit pulse density modulated PDM signal by a multibit multiplier to obtain a multibit number stream, which is reconverted into a single-bit PDM signal by a second digital sigma-delta modulator, as to the signal-to-noise ratio. Thus the most significant factor in the total signal-to-noise is the noise level of the first sigma-delta modulator, by which the PDM signal was originally generated. In the subsequent second sigma-delta modulator, the PDM signal can then be attenuated as much as is the difference between SNR performance of the modulators without any decrease in the total signal-to-noise ratio.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: July 29, 2003
    Assignee: Atmel Corporation
    Inventors: Lauri Lipasti, Arhippa Kovanen
  • Patent number: 6596604
    Abstract: A method for preventing thermal stress and the shifting of alignment marks during semiconductor processing including providing a semiconductor wafer having a first selected portion for fabricating integrated circuitry and a second non-fabrication portion including alignment marks, introducing dopant into said first and second portions, when dopant is required to be introduced in said first portion, thereby increasing radiant energy absorptivity and decreasing radiant energy transmissivity in both portions such that the thermal emissions detected.at the portions result in no significant temperature variation between portions during heating. Therefore thermal stress and shifting of alignment marks are prevented.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: July 22, 2003
    Assignee: Atmel Corporation
    Inventors: Bohumil Lojek, Michael D. Whiteman
  • Patent number: 6595565
    Abstract: A carpet-stretching device for stretching a carpet laid over a floor onto a fixing strip. The device includes: a shank having a first end and a second end; a head portion carrying a plurality of carpet engaging pins provided at the first end of the shank; and an end portion provided at the second end of the shank. The shank, head portion, and end portion are generally linearly arranged so that the application of a force to the end portion, in use, tends to drive the carpet in a direction that is generally parallel to the device rather than towards the floor.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: July 22, 2003
    Assignee: Stikatak Limited
    Inventors: John Whiting, Stephen L. Szabo, David Hume
  • Patent number: 6597212
    Abstract: A phase interpolator circuit that produces 2m phase resolution elements using a control signal that has less than m bits. The circuit combines the function of a divide-by-N circuit with a phase interpolation circuit enabled by the use of a higher-speed clock as an input. By performing phase interpolation at a high speed and then slowing down the speed for the subsequent circuits, the phase resolution increases and fewer control bits are required.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: July 22, 2003
    Assignee: Neoaxiom Corporation
    Inventors: David Y. Wang, Yu-Chi Cheng
  • Patent number: 6597077
    Abstract: A two-phase step motor with bifilar winding around the stator poles is connected to phases &agr; and &bgr; (90° apart) of a two-phase driver in a manner that maximizes torque at medium speed operation and minimizes vibrations. In particular, the coils that are wound around different groups of stator poles are connected in series. In one set, both coils are connected in a forward sense around the stator, while in the other set, the two coils are connected in opposite senses. All coils are energized in every phase of a pulse cycle. The properties are intermediate between that of convention series and parallel stator coil connections.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: July 22, 2003
    Inventors: Ted T. Lin, Ryan C. Lin
  • Patent number: 6597749
    Abstract: A pulse monitoring circuit monitors the pulse length of both the logic high pulse and logic low pulse of a received digital sequence. The pulse lengths are compared with a preferred transition window, and if the pulses transition within the preferred transition window then they are categorized as good pulses. The pulse monitoring circuit issues an enable signal only when at least two consecutive good pulses are received. The pulse length is determined by means of a reference voltage, a first faster linear voltage ramp, and a second slower linear voltage ramp. The two linear voltage ramps are initiated in response to a logic change of the received digital sequence and continue to raise their outputs until the received digital sequence changes state once again. The values of the two linear voltage ramps at the time of the second state change are compared with the reference voltage.
    Type: Grant
    Filed: November 19, 1999
    Date of Patent: July 22, 2003
    Assignee: Atmel Corporation
    Inventor: Gaetan J. J. Bracmard
  • Patent number: 6597603
    Abstract: A dual mode high voltage power supply circuit using an external high voltage connected through an internal high voltage switch which determines whether the memory blocks of a non-volatile memory circuit are programmed in a first mode from an internal high voltage charge pump or are programmed in a second mode from an external high voltage power supply connected in parallel to the internal high voltage charge pump. When the dual mode high voltage power supply circuit is operating in the first mode using only its internal change pump high voltage, it operates in a low power, low-speed mode, programming only one or two bits at a time but allowing the charge pump area on the die to be small.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: July 22, 2003
    Assignee: Atmel Corporation
    Inventors: Emil Lambrache, George Smarandoiu
  • Patent number: 6590495
    Abstract: An automobile distance warning and alarm system (ADWAS) in which the warning system is armed when the vehicle exceeds a threshold speed. The vehicle speed is used, along with road or weather conditions, to determine a safe vehicle separation time and corresponding distance. A range finder then determines the actual separation distance between the driver's vehicle and a forward or following vehicle. If the safe separation distance is not maintained for a selected dead time interval, the driver is alerted by an alarm, which may be both an audible and visual alarm. The driver of a following vehicle is also alerted by a rear indicator light.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: July 8, 2003
    Inventor: Iraj Behbehani
  • Patent number: 6574957
    Abstract: A system for using tidal or wave action to compress air at a high pressure and produce electricity. The system includes a piston contained in a chamber including an air intake port. The chamber is connected to an air storage tank through a valve. A moveable power transfer shaft contained in a sleeve guide has a float disposed on ocean waves providing motion to the shaft. A lever arm is contacted by the power transfer shaft at one end and is connected to the piston at another end. As the power transfer shaft is upwardly displaced by the float, so is the lever arm at one end causing the piston to compress air within the chamber at another end. When a dual piston embodiment is employed, air is compressed upon upward and downward movement of the power transfer shaft. In an alternative embodiment, a gear mechanism is employed to transfer the linear movement of the power transfer shaft to the pistons. In both the lever and the gear embodiments, the air is compressed and stored at a high pressure in a storage tank.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: June 10, 2003
    Inventor: Donald U. Brumfield
  • Patent number: 6577008
    Abstract: A redistribution metallization scheme combines solder bumps and wire bond pads in addition to existing bond pads to enhance the connectivity of a semiconductor device, especially in flip-chip applications. The fabrication method includes forming the additional bond pads during the redistribution deposition step. The metals used in the redistribution layer provide a solderable surface for solder bumping and a bondable surface for wire bonding.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: June 10, 2003
    Assignee: Atmel Corporation
    Inventors: Ken M. Lam, Julius A. Kovats
  • Patent number: 6551839
    Abstract: A capillary valve, connector and router where one or more cylindrical fibers, which may be capillaries, plugged capillaries, optical fibers, or the like, including at least one capillary tube are contained in a first bundle of fibers that terminates at a first face. A second cylindrical bundle of fibers also containing one or more fibers including at least one capillary tube terminates in a second face abutting the first face. A fastener or adapter holds the members together with faces in mutually biased alignment. Connection of a plurality of macroscale pumps enables push-pull fluid motion, with routing, in a capillary system formed by a plurality of fibers coupled by switches, connectors and routers. Chemical reactions, separations and analysis may be carried out with microliter volumes or smaller.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: April 22, 2003
    Assignee: Amersham Biosciences Corp.
    Inventors: Stevan B. Jovanovich, Gregory J. Ronan, David J. Roach, Richard F. Johnston
  • Patent number: 6550676
    Abstract: A system and method for transferring data between a read/write apparatus having a shuttle powered by a single motor supporting a hybrid data storage card and having optical and electrical data heads. The hybrid data storage card has an integrated circuit module and an optical memory unit both on a single side of the hybrid card. Electrical signal communication occurs when a gap between the shuttle and a support connected to the electrical head is closed such that the electrical head is able to align with the integrated circuit module. Optical signal communication occurs between the optical data head and optical memory unit when the gap is formed and maintained between the shuttle and the support connected to the electrical head such that the shuttle is able to move linearly without interference from the support.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: April 22, 2003
    Assignee: Drexler Technology Corporation
    Inventor: Richard M. Haddock
  • Patent number: 6545532
    Abstract: A timing recovery circuit in a QAM demodulator which uses a symbol rate continuously adaptive interpolation filter. The method of interpolation used in the present invention is defined as a function of time per interpolation interval, rather than as a function of time per sampling interval as is commonly implemented in the prior art. This allows the interpolation filtering to be totally independent of the symbol rate in terms of complexity and performance and provides a better rejection of adjacent channels, since the interpolator rejects most of the signal outside the bandwidth of the received channel.
    Type: Grant
    Filed: April 17, 2000
    Date of Patent: April 8, 2003
    Assignee: Atmel Corporation
    Inventors: Khaled Maalej, Emmanuel Hamman, Amaury Demol, Yannick Levy
  • Patent number: 6543678
    Abstract: A method for brazing beryllium-aluminum alloy members to form a beryllium-aluminum alloy assembly and coating the beryllium-aluminum alloy assembly in which an aluminum-silicon based braze alloy is placed between the beryllium-aluminum members at the locations for forming braze joints. The aluminum-silicon based braze alloy is surrounded by a brazing flux comprising aluminum fluoride. The beryllium-aluminum alloy members and the aluminum-silicon based braze alloy are heated to form the beryllium-aluminum alloy assembly. Oxidized surfaces appearing on the beryllium-aluminum alloy members are removed. Thereupon, the beryllium-aluminum alloy assembly is coated by plasma deposition of alumina-titania powder.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: April 8, 2003
    Assignee: The Peregrine Falcon Corporation
    Inventors: John L. Emmons, Robert Hardesty
  • Patent number: 6541284
    Abstract: An IC chip package for an image sensitive, integrated circuit semiconductor die incorporates all the components typically found in an imaging module of an electronic camera. The IC chip package consists of a plastic substrate base for holding an image sensor die and a separate, plastic upper cover for encapsulating the image sensor die and holding a filter glass, an optical lens, and providing an aperture for the optical lens. The upper cover has a lower shelf for holding the optical lens in alignment with the aperture opening over the image sensor die, and has an upper shelf for holding the filter glass over the optical lens. The lens is attached to the lower shelf using UV cure adhesive, and its focal distance to the image sensor die is determined by first electrically activating the image sensor die, adjusting the lens position to identify the optimal focus sharpness, and then applying UV light to activate the UV cure adhesive and hold the lens in focus.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: April 1, 2003
    Assignee: Atmel Corporation
    Inventor: Ken M. Lam
  • Patent number: 6537895
    Abstract: A method of forming a shallow trench isolation region in a silicon wafer which results in the elimination of long range slip dislocations in the wafer and reduces leakage current across the isolation regions. Long shallow trenches are formed in a silicon wafer at a 45 degree angle to the (111) plane of the wafer. This is achieved by moving the primary flat of the wafer to the (100) plane prior to the formation of the trenches, which causes the bottom edges of the long trenches to intersect with several (111) planes, so that stresses do not propagate along any one single (111) plane. The trenches are then filled with an insulative material, such as oxide.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: March 25, 2003
    Assignee: Atmel Corporation
    Inventors: Eric R. Miller, Stephen R. Moon
  • Patent number: D476032
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: June 17, 2003
    Assignee: Chameleon Books & Journals, Inc.
    Inventor: Emmanuel Marchand