Patents Represented by Attorney, Agent or Law Firm Thompson & Knight, LLP
  • Patent number: 7668715
    Abstract: A method of performing quantization in an audio encoder includes determining a number of bits available in a frame of encoded audio data. Determinations are also made for the maximum transform coefficient value and a distribution of transform coefficient values across the transform coefficient spectrum being encoded. A an estimate for an initial quantization step value is determined from the number of available bits in the frame, the maximum transform coefficient value, and the distribution of coefficient values across the coefficient spectrum.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: February 23, 2010
    Assignee: Cirrus Logic, Inc.
    Inventors: Ravindra Ramkrishna Chaugule, Sachin P. Ghanekar
  • Patent number: 7646968
    Abstract: An embedded digital versatile disk recording system operable to selectively record a menu with a user generated background image on a digital versatile disk.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: January 12, 2010
    Assignee: Magnum Semiconductor, Inc.
    Inventors: Samuel C. Wang, Matthieu C. A. Jeanson, Jeremy V. Alves
  • Patent number: 7644656
    Abstract: Conventional type liquefier appliance that incorporates an anti-drip system consisting of a “T”-shaped spout seal, besides the inclusion of a series of non-slip strips on the connecting gears between the drive unit and the rotary elements, which enable it to come to a sudden stop without the inertia of said elements forcing them in an upward direction, furthermore the grater disc is not fixed to the drive element by a through-screw but rather said screw is welded to its under side, while in addition the push piston terminates in a concavity which engages the piece to be liquefied during use and wherein said piston may be replaced by a feed hole reducer piston.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: January 12, 2010
    Assignee: Zumex Maquinas Y Elementos, S.A.
    Inventor: Felipe Maria Moreno Esteve
  • Patent number: 7639002
    Abstract: A method of testing an integrated circuit including a plurality of test nodes includes initiating a test mode and, during a first time interval of the test mode, stepping a level of a supply current of the integrated circuit to a calibration level. Parameters are observed at the plurality of test nodes to detect errors during a second time interval of the test mode and the level of the supply current selectively stepped in response to a number of errors detected. The level of the supply current is decoded to identify the detected errors.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: December 29, 2009
    Assignee: Cirrus Logic, Inc.
    Inventors: Murari Kejariwal, Prisad Ammisetti, Axel Thomsen, John Laurence Melanson
  • Patent number: 7613615
    Abstract: A data de-shuffler includes a buffer having a set of addressable locations for storing data and control circuitry for de-shuffling a sequence of shuffled data samples. The control circuitry stores a first data sample of the sequence of shuffled data samples at a first location in the buffer with a first address generated from an entry in a look up table and stores a second data sample at a second location in the buffer with a second address generated by incrementing from the first address by a selected incrementation value. The first and second locations in the buffer place the first and second samples in corresponding positions in an un-shuffled sequence of samples.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: November 3, 2009
    Assignee: Magnum Semiconductor, Inc.
    Inventors: Akhtar Mahmood, Cheng-Tie Chen, Ting-Chung Chen
  • Patent number: 7605723
    Abstract: Mode selection circuitry selects one of a plurality of operational modes supported by an integrated circuit by detecting a selected connection between a first terminal of the integrated circuit and a mode control terminal of the integrated circuit. Other including a mode control terminal coupled to an integrated circuit for receiving a mode selection signal and mode select circuitry for selecting an operational mode of the integrated circuit in response to a frequency of the mode control signal.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: October 20, 2009
    Assignee: Cirrus Logic, Inc.
    Inventors: Kartik Nanda, Aryesh Amar
  • Patent number: 7538824
    Abstract: A method of deinterlacing includes generating a deinterlaced display frame including a reference field of lines of display pixels of a first parity and a generated field of lines of display pixels of a second parity. A frame motion map is generated which includes bits representing a presence of motion or an absence of motion at the display pixels of the reference and generated fields. Testing is performed for the presence of motion or the absence of motion at a selected display pixel of the reference field utilizing the frame motion map. In response to detecting a presence of motion at the selected display pixel of the referenced field, replacing a pixel value corresponding to the selected display pixel with a pixel value generated by interpolating between display pixel values corresponding to neighboring display pixels in the generated field.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: May 26, 2009
    Assignee: Magnum Semiconductor, Inc.
    Inventors: Sanjay R. Pillay, Brian F. Bounds, William Lynn Gallagher
  • Patent number: 7538823
    Abstract: A method of separating a chroma data component from a video data stream includes determining a phase relationship between a color burst in digital video data samples of a composite video signal and a local clock signal which processes the digital video data samples. In response to determining the phase relationship, interpolation filtering is performed on the digital video data samples corresponding to first and second display lines to generate phase aligned video data samples. Adaptive filtering is then performed utilizing the phase aligned video data samples corresponding to the first and second display lines to separate the chroma component from the digital video data samples corresponding to the first display line.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: May 26, 2009
    Assignee: Cirrus Logic, Inc.
    Inventors: Rahul Singh, James Antone, John Laurence Melanson, Daniel O. Gudmundson
  • Patent number: 7522214
    Abstract: A method of adaptive deinterlacing of video data includes generating a selected pixel value at a given pixel position of a current interlaced field by either weaving a pixel value from another interlaced field, when no motion is detected at the pixel position, or by interpolating between other selected pixel values of the current field, when motion is detected at the pixel position. When the pixel value is generated by weaving, a test for feathering is performed. If feathering is detected, a further check is performed for motion at the pixel position over a selected number of preceding fields. In the absence of motion over the preceding fields, the weaved pixel value is utilized as the selected pixel value. If motion is detected over the preceding fields, interpolation is performed between selected pixel values of the current field to generate the selected pixel value.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: April 21, 2009
    Assignee: Magnum Semiconductor, Inc.
    Inventors: Sanjay R. Pillay, Brian F. Bounds, William Lynn Gallagher
  • Patent number: 7521951
    Abstract: A method of testing an internal block of an integrated circuit includes initiating a test mode and verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. A test signal is selectively output from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: April 21, 2009
    Assignee: Cirrus Logic, Inc.
    Inventors: Murari Kejariwal, John Laurence Melanson, Ammisetti V. Prasad, Sherry Xiaohong Wu
  • Patent number: 7484356
    Abstract: A translating cowl composed of two sub-structures forms the thrust reverser for a turbofan engine. The two sub-structures form the rear part of a nacelle, are translatable, and have operative and inoperative modes of operation. The operative mode is used for direct or reverse thrust operation of the engine and the inoperative mode is used for access to the engine.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: February 3, 2009
    Assignee: Aeronautical Concepts of Exhaust, LLC
    Inventor: Jean-Pierre Lair
  • Patent number: 7475116
    Abstract: A method of increasing the likelihood an electronic message will be opened by a targeted recipient includes determining a time zone corresponding to an address of a targeted recipient and accessing an opening history for a set of electronic mail recipients within a domain including the targeted recipient. From the time zone and the opening history at least one of a time and a day are recommended for sending an electronic message to the target recipient to increase likelihood that the electronic message will be opened.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: January 6, 2009
    Inventor: Donald William Hay
  • Patent number: 7456765
    Abstract: A system for determining a data converter clock operating mode includes measurement circuitry which measures a master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency, the frequency ratio, and a characteristic of an additional data clock signal to an operating mode of the data converter. In another embodiment, the mapping system maps measurements of the master clock frequency alone to a data converter operating mode. In a further embodiment, the measurement circuitry measures the master clock frequency of a master clock signal, which is received directly from a master clock signal source without a modification in the master clock frequency.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: November 25, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Bruce Eliot Duewer, John Laurence Melanson, Kartik Nanda
  • Patent number: 7450184
    Abstract: A method of detecting a stream of video data generated utilizing a pull-down technique includes receiving a sequence of fields of interlaced video data. For each pair of a plurality of pairs of the fields of interlaced video in the sequence, pixel values corresponding to pixel positions of pixel lines of a first parity of a first field of the pair of fields are weaved with pixel values corresponding to pixel positions of pixel lines of a second parity of a second field of the pair of fields. For each pixel value corresponding to each pixel position of each pixel line of the second field of the pair of fields after weaving, a check is made for feathering at the corresponding pixel position due to motion.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: November 11, 2008
    Assignee: Magnum Semiconductor, Inc.
    Inventors: Sanjay R. Pillay, Brian F. Bounds, William Lynn Gallagher
  • Patent number: 7446686
    Abstract: A method of operating a delta-sigma data converter includes receiving an input signal at an input of a delta-sigma modulator having a loop filter including a plurality of integrator stages, a quantizer for generating a quantized output code from outputs of the integrator stages, and a feed-back loop coupling a feed-back signal from the output of the quantizer to the input of the delta-sigma modulator. The input signal is converted to quantized output codes during a conversion period including a plurality of integrator cycles in which at least one of the integrator stages is held in reset for at least one integration cycle at the start of the conversion period to maintain stability of the modulator over a wider range of levels of the input signal.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: November 4, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Timothy Rueger, Stephen Timothy Hodapp
  • Patent number: 7433370
    Abstract: A method and data structure for transmitting data in a networked system having a shared transmission medium that includes generating a plurality of virtual packets each containing information for delivery to at least one selected terminal in the networked system via the shared medium and generating a map field having control information for controlling the delivery of the virtual packets. The method and data structure also include forming a physical packet for transmission across the shared transmission medium, the physical packet including a control field and the plurality of virtual packets such that overhead associated with the control field and medium access is amortized over the plurality of virtual packets.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: October 7, 2008
    Inventor: LaRoy Tymes
  • Patent number: 7424544
    Abstract: A method and system for improving networking performance in networks based on lossy channels. A selected file system call 109 is redirected by sending a file request to a server over a first protocol. Data is received from the server in response to the file request over a second protocol.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: September 9, 2008
    Assignee: Cirrus Logic, Inc.
    Inventors: Rajesh Bhagwat, Mircea Ouatu-Lascar
  • Patent number: 7420626
    Abstract: A method of detecting a change in a sequence of video data fields generated from a progressive scan source includes receiving first and second interlaced fields of a corresponding progressive scan frame from a sequence of interlaced fields generated from progressive scan source. Pixel values corresponding to pixel positions of pixel lines of a first parity of the first field are weaved with pixel values corresponding to pixel positions of pixel lines of a second parity of the second field. For each pixel value corresponding to each pixel position of each pixel line of the second field after weaving, a check is performed for the corresponding pixel position for feathering due to motion. A number of detected pixel positions with feathering due to motion is counted and compared against a threshold.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: September 2, 2008
    Assignee: Magnum Semiconductor, Inc.
    Inventors: Sanjay R. Pillay, Brian F. Bounds, William Lynn Gallagher
  • Patent number: 7414671
    Abstract: A method interpolating pixel values includes calculating a difference value between pixel values corresponding to a first display pixel on a first display line and a second display pixel on a second display line, the first and second display pixels defining a possible edge angle of an object on a display. Another difference value is calculated between pixel values corresponding to a third display pixel of the first display line and a fourth display pixel of the second display line, the third and fourth display pixels defining a second angle on the display.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: August 19, 2008
    Assignee: Magnum Semiconductor, Inc.
    Inventors: William Lynn Gallagher, Brian F. Bounds, Sanjay R. Pillay
  • Patent number: D581828
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: December 2, 2008
    Assignee: TXDC, L.P.
    Inventor: Siddharth Ashok Mehta