Abstract: A rail switch is provided having an improved throw rod to enable testing with damaging the switch. The throw rod includes a housing on its length, with a piston and spring located within the housing. A locking pin locks movement of the piston during normal operation, causing the throw rod to act as a solid rod as previously used in the art. The locking pin can be removed during gap testing, to enable a small amount of play in the length of the rod. This eliminates the stress caused on the switch by testing.

Abstract: A feed-forward operational amplifier including a dedicated summer circuit for summing a signal generated by a first amplifier stage of a feed-forward amplifier and a signal received from an external source to generate a sum signal and a second amplifier stage coupled to the summer circuit and receiving the sum signal. The second amplifier stage realizes a pole-zero doublet to decrease a unity gain frequency of the feed-forward operational amplifier.

Abstract: A method of generating comfort noise in a communications includes selecting a packet of data from a stream of packets being received across a communications network, the packet comprising a selected number of data samples. Ones of the data samples from the selected packet are played out in a sequence as comfort noise to fill a dead gap. The sequence is reversed when a randomly selected sample in the packet is reached and corresponding ones of the data samples are transmitted across the network as comfort noise after the order is reversed.

Abstract: A medium access control (MAC) layer for a node of a wireless local area network, which may be used in embedded, host and stand-alone applications, includes a hardware layer and a software layer. The hardware layer is configured to perform time-critical tasks and the software layer is configured to perform non-time critical tasks. The software layer includes multiple modules, such as one or more of a host communication agent, a bridging layer, a network management support module, a SBM-to-TAME conversion module, and a rate estimation module. Further, the software layer acts as the source of and the destination of MAC Service Data Units and is configured as a hierarchical structure in which functional unit blocks for associated elements of the hardware layer communicate with an application layer through respective device drivers and managers. Device drivers and managers communicate through a device manager layer.

Abstract: Admission to a computer network is provided by having a network device listen to a communication channel communicatively coupling two or more components of the computer network. In some cases, the network device may then transmit a connection request to a controller of the computer network within a designated time slot of the communication channel. In other cases, the connection request may be transmitted without requiring the network device to be polled. The connection request may be confirmed by transmitting the connection request from the controller to network device periodically, until a response from the first network device is received by the controller. Upon confirmation, the controller may send to the network device, a connection agreements package, which includes information regarding time slots within the communication channel to be used by the controller for transmitting information to the first network device.

Abstract: A clock generator includes input circuitry for receiving an input signal and generating a memory address therefrom. A memory stores digital data indexed by the memory address which represents at least a portion of an analog clock. A digital to analog converter converts data retrieved from the memory to generate the analog clock which is then filtered by a filter and then converted into digital output clock.

Abstract: A sample and hold circuit including a sampling capacitor for storing a sample of an input signal, an output stage for outputting the sample stored on the sampling capacitor; and input circuitry for sampling the input signal and storing the sample on the sampling capacitor. The input circuitry includes an autozeroing input buffer which selectively samples the input signal during a first operating phase and holds a sample of the input signal during a second operating phase. The autozeroing input buffer cancels any offset error. The input circuitry also includes switching circuitry for selectively coupling the sampling capacitor with an input of the sample and hold circuitry during the second operating phase and to an output of the autozeroing input buffer during the first operating phase.

Abstract: An improved tapping sleeve includes a first sleeve member having an outlet aperture, a second sleeve member, and a unitary gasket. An outlet retaining ring is positioned around the outlet aperture. A pair of end retaining lips are positioned on inner surfaces of the first and second sleeve members at opposing ends of the sleeve members. The gasket includes a gasket outlet having a pair of tapered surfaces on opposing longitudinal sides of the gasket outlet. The gasket, when positioned on a pipe in an un-stretched, uncompressed position subtends an arc of less than 360 degrees, creating a gap in the gasket. As the first and second sleeve members are connected, the outlet retaining lip engages armor members on the gasket, thereby circumferentially stretching the gasket and closing the gap. The tapered surfaces and the outlet retaining lip prevent excessive gasket flow into the outlet aperture.

Abstract: A lifting apparatus for use in lifting a trailer from a railcar, wherein the trailer includes a tandem rear axel with wheel assemblies having tires coupled thereto, for use in combination with an overhead crane having a plurality of lifting shoes for engaging the trailer at a plurality of lifting points. The lifting apparatus includes a connector member for connecting the lifting apparatus to a lower portion of particular ones of the plurality of lifting shoes and a retaining member for engaging the tandem rear axel and a particular one of the wheel assemblies in order to secure the particular one of the wheel assemblies in a fixed position and to bear the weight of the tandem rear axel and the wheel assemblies. The lifting apparatus also includes an adjustment member for determining an amount of engagement between the retaining member and the tandem axel and the particular one of the wheel assemblies.

Abstract: A driver circuit with power-down transient suppression includes an amplifier for driving a load coupled to an output of the amplifier, a ramp-down voltage generator having a capacitor and a resistor for generating a ramp-down voltage during power-down of the amplifier, and a differential transistor pair responsive to the ramp-down voltage for pulling-down current at the output of the amplifier during power-down of the amplifier.

Abstract: A method of processing digital audio data includes receiving an input stream of audio data having a first quantization and a high oversampling rate. The input stream is requantized in a first processing block at the high oversampling rate to a second quantization. The requantized stream of audio data is processed in a second processing block at the high oversampling rate and the second quantization.

Abstract: An improved freight container for use in intermodal freight transportation systems that includes lift castings having a top lift aperture located on the lift casting at an outboard position, such that when other containers are stacked on top of the improved container, loads are properly distributed through reinforcement beams of the improved container, thereby substantially reducing bending stresses in the improved container, substantially reducing the possibility fatigue failure of the improved container, and reducing the costs of maintenance and inspection of the improved container.

Abstract: A system for determining a data converter operating mode includes measurement circuitry operable to measure a master clock frequency of a master clock signal and measure a frequency ratio between a data clock frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter utilizing an explicit formula. In a further embodiment, the mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter utilizing a lookup table. In an additional embodiment, the mapping system tests an available set of operating modes, independent of any previous tests, to determine a suitable operating mode for the data converter.

Abstract: A charge pump including a differential pair of transistors for controlling a current at a charge pump output node and a replica bias generator for selectively driving a first transistor of the differential pair of transistors into a fully-on state and a second transistor of the differential pair of transistors into a weak inversion state.

Abstract: Mode detection circuitry includes first detection circuitry which detects the presence of a first input signal selectively presented at a first terminal for a first selected time duration and, in response, selectively generating a first control signal indicative of a first mode. Second detection circuitry detects the presence of a second input signal selectively presented at a second terminal for a second selected time duration and, in response, selectively generating a second control signal indicative of a second mode. Control circuitry configures the second terminal as an output terminal in the first mode and as an input terminal in the second mode in response to the first and second control signals.

Abstract: A system for determining a data converter operating mode including measurement circuitry operable to measure a master clock frequency by comparing a frequency of a master clock signal and a frequency of a fixed frequency clock signal and operable to measure a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In one particular embodiment, the fixed frequency clock signal is provided by an oscillator. In a further embodiment, the master clock signal is generated by multiplying the frequency of another clock signal.

Abstract: The time required to measure 1/f noise for a device, such as an integrated circuit, can be shortened by applying offset to a chopper stabilized circuit and then using offset removal as a surrogate measure for 1/f noise performance.

Abstract: A decoding method includes extracting a preselected number of bits from a bitstream to be decoded, accessing a table entry of a table using an index generated in response to the extracted bit, and if a first value in the table entry indicates a second value in the table entry comprises a decoded result, retrieving the decoded result.

Abstract: Memory address decoder circuitry including a decoder for activating a corresponding memory access control conductor in response to registered address bits. An address register stores received address bits for presentation to the inputs of the decoder and includes reset circuitry for resetting the outputs of the address register to an inactive state during an inactive time period to reduce transition glitches in the decoder during latching in a subsequent active period.

Abstract: An optical disk pickup system includes an array of photodiodes 101 for converting photons reflected from an optical disk into a plurality of electrical signals each representing a channel. Driving circuitry 407, 408 drives at least one of the electrical signals as a current across a conductor of a flexible cable 403. A low impedance load 404 converts the electrical signal driven across the conductor as a current into a voltage for further processing.